| Patent application number | Description | Published |
|---|
| 20080211035 | Semiconductor memory device and method of manufacturing the same - A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell. | 09-04-2008 |
| 20080291769 | Multiport semiconductor memory device - In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD-Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented. | 11-27-2008 |
| 20090052262 | SEMICONDUCTOR MEMORY DEVICE - A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller. | 02-26-2009 |
| 20090091970 | SEMICONDUCTOR MEMORY DEVICE - Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell. | 04-09-2009 |
| 20090141569 | SEMICONDUCTOR MEMORY DEVICE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 06-04-2009 |
| 20090244950 | SEMICONDUCTOR MEMORY DEVICE HIGHLY INTEGRATED IN DIRECTION OF COLUMNS - First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns. | 10-01-2009 |
| 20090268531 | Semiconductor memory device with adjustable selected work line potential under low voltage condition - A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage. | 10-29-2009 |
| 20090323398 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor. | 12-31-2009 |
| 20110032750 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor. | 02-10-2011 |
| 20110134706 | SEMICONDUCTOR MEMORY DEVICE - A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller. | 06-09-2011 |
