| Patent application number | Description | Published |
|---|
| 20090204380 | Performance evaluation simulation - A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based. | 08-13-2009 |
| 20100204975 | Simulation method, electronic apparatus design method, and simulation apparatus - A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user. | 08-12-2010 |
| 20100284234 | MEMORY CONTROL METHOD AND MEMORY CONTROL DEVICE - A memory control method that carries out first-in first-out access control for a memory having a plurality of storage areas, including: selecting, as write positions, an address of a storage area in a storage block having at least one or more storage areas and an address of a storage area in any one of a plurality of redundant blocks that are made redundant with respect to the storage block and have at least one or more storage areas when the write positions are selected to write data to the memory; and selecting, as read positions, an address of a storage area of the storage block and an address selected by the selecting of the write position from among the addresses of a plurality of the redundant blocks when the read positions are selected to read data written by the writing of the data to the memory. | 11-11-2010 |
| 20100325184 | DIGITAL SIGNAL PROCESSING APPARATUS AND DIGITAL SIGNAL PROCESSING METHOD - A digital signal processing apparatus includes a frame generator configured to generate a plurality of frames from a row of sample data of a time-domain, a part of each frame overlapping with adjoining frames, a Fourier transform unit configured to transform at least one of the generated frames into a frequency domain by Fourier transformation, an addition unit configured to add predetermined frequency characteristic to the transformed frame, and an inverse Fourier transform unit configured to transform the added frame into the time-domain by inverse Fourier transformation and to delete the overlap of the frame of the time-domain transformed. | 12-23-2010 |
| 20100329697 | DIGITAL COHERENT RECEIVING APPARATUS - A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator. | 12-30-2010 |
| Patent application number | Description | Published |
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| 20090253434 | Base Station And Method For Reducing Transfer Delay - A disclosed base station for transferring, to a user terminal, a series of packet data received from a higher-level network, includes a determining unit configured to, when the user terminal is handed over to a handover destination base station due to movement of the user terminal, determine according to a transfer delay-related characteristic of the series of packet data whether data forwarding of the series of the packet data to the handover destination base station is not to be performed. | 10-08-2009 |
| 20090286537 | MOBILE SWITCHBOARD, MOBILE UNIT, MOBILE COMMUNICATION SYSTEM, AND POSITION- REGISTRATION EXTENDING METHOD - A mobile unit transmits a request for position registration to a network when moving from a first area to a second area. When the number of incoming calls does not exceed a threshold and the number of movements between the first area and the second area exceeds a threshold, a mobile switchboard combines the first area and the second area into an extended area, and informs the mobile unit of the extended area. | 11-19-2009 |
| 20110319078 | MOBILE SWITCHBOARD, MOBILE UNIT, MOBILE COMMUNICATION SYSTEM, AND POSITION- REGISTRATION EXTENDING METHOD - A mobile unit transmits a request for position registration to a network when moving from a first area to a second area. When the number of incoming calls does not exceed a threshold and the number of movements between the first area and the second area exceeds a threshold, a mobile switchboard combines the first area and the second area into an extended area, and informs the mobile unit of the extended area. | 12-29-2011 |
