| Patent application number | Description | Published |
|---|
| 20080312890 | SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD - Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output. | 12-18-2008 |
| 20090276740 | VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT - In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output. | 11-05-2009 |
| 20090276741 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output. | 11-05-2009 |
| 20090287965 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 11-19-2009 |
| 20090319246 | DETECTION PROGRAM, DETECTING DEVICE, AND DETECTING METHOD - A computer-readable recording medium stores a detection program. The detection program causes a computer to execute performing the scenario model and assigning a predetermined test value to the input variable of the scenario model; performing the implementation model and assigning the test value to the input variable of the implementation model; analyzing a structure of read and write processes for each input variable of the scenario model; analyzing a structure of read and write processes for each input variable of the implementation model; comparing a value of the output variable associated with performing the scenario model and a value of the output variable associated with performing the implementation model; and comparing the structure related to the scenario model and that related to the implementation model to detect a difference between the two models. | 12-24-2009 |
| 20090319829 | PATTERN EXTRACTION METHOD AND APPARATUS - A test pattern extraction method includes obtaining an identifier of a processing executed for a test pattern by a verification target, and storing the identifier of the processing into a test result data storage device in association with the test pattern; calculating a distance between the test patterns whose identifiers of the processing are different each other and which are stored in the test result data storage device, identifying, for each pair of the identifiers of the processing, a pair of the test patterns whose distance satisfies a predetermined condition, and storing data of the identified pair of the test patterns into a pattern data storage device. | 12-24-2009 |
| 20110138228 | VERIFICATION COMPUTER PRODUCT AND APPARATUS - A non-transitory, computer-readable recording medium stores therein a verification program that causes a computer to execute detecting from a structure expressing a group of scenarios for verifying an operation of a design under verification and by hierarchizing sequences for realizing the operation as nodes, a similar node similar to a faulty node representing a sequence in which a fault has occurred; generating a string of sequences represented by a group of nodes on a path starting from a start node of the structure to the detected similar node; and outputting the generated string of sequences. | 06-09-2011 |
| 20110239172 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 09-29-2011 |
