| Patent application number | Description | Published |
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| 20090069445 | PROPOFOL-CONTAINING FAT EMULSIONS - This invention provides a propofol-containing fat emulsion preparation including: 0.1 to 2 w/v % of propofol, 10 to 20 w/v % of an oily component, and 2 to 5 w/v % of an emulsifier, the weight of the oily component being in the range of about 5 to about 200 times the weight of propofol, the weight of the emulsifier being in the range of about 0.9 to about 50 times that of propofol, and the average size of emulsion particles being 180 nm or less, and a method for preparing the same. Propofol-containing fat emulsion preparation of this invention alleviates the vascular pain that occurs during the administration thereof without incorporating a local anesthetic, such as lidocaine or the like, therein. | 03-12-2009 |
| 20090192230 | Propofol-containing fat emulsion preparation - The present invention provides a propofol-containing fat emulsion that can be administered with reduced vascular pain without incorporating a local anesthetic such as lidocaine; and a process for producing the same. The fat emulsion comprises 0.1 to 5 w/v % of propofol, 2 to 20 w/v % of an oily component, 0.4 to 10 w/v % of an emulsifier and 0.02 to 0.3 w/v % of at least one compound selected from the group consisting of cyclodextrins, cyclodextrin derivatives and pharmacologically acceptable salts thereof, and is in the form of a fat emulsion. | 07-30-2009 |
| 20110100861 | PLASTIC AMPULE AND COLORED PLASTIC CONTAINER - An object of the present invention is to provide a plastic ampule capable of suppressing volatilization and scattering of a drug solution and elution of plastic compounding ingredients into the drug solution, as well as suppressing whisker formation and deformation and damage of an opening when the plastic ampule is opened. A plastic ampule | 05-05-2011 |
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| 20100091590 | Semiconductor memory apparatus - A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal. | 04-15-2010 |
| 20110019493 | Semiconductor memory device - Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit. | 01-27-2011 |
| 20110063896 | Semiconductor memory device - A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array. | 03-17-2011 |
