| Patent application number | Description | Published |
|---|
| 20090086962 | ENCRYPTION OPERATING APPARATUS - Valid code data and invalid code data are alternately input to a register that fetches data synchronously with a clock signal. A state of a data value input to the register is monitored. Each time when it is determined that the data is stabilized by the valid code data, the register holds the valid code data. | 04-02-2009 |
| 20110131470 | MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area. | 06-02-2011 |
| 20110246791 | MEMORY CHIP, INFORMATION STORING SYSTEM, AND READING DEVICE - According to one embodiment, a memory chip, which is connected to a writing device that writes data and to a reading device that reads data, includes: a memory including a first area that is a predetermined data storage area; a second encryption key generating unit that receives second key information stored in the reading device and generates a third key; and a sending unit that transmits, to the reading device, second encrypted data obtained by encrypting data stored in the memory using the third key. The second encrypted data is received by the reading device and is decrypted by using a fourth key that is stored in the reading device and that corresponds to the third key. | 10-06-2011 |
| 20110311048 | CRYPTOGRAPHIC OPERATION APPARATUS, STORAGE APPARATUS, AND CRYPTOGRAPHIC OPERATION METHOD - According to one embodiment, the cryptographic operation apparatus performs a cryptographic operation using first and second key data and includes an initial mask value creating unit that creates the initial mask value using the second key data and data information. In addition, the cryptographic operation apparatus further includes a mask value updating unit that creates the mask value using the initial mask value and a mask value storing unit that stores and outputs the initial mask value and the created mask value. In addition, the encryption is performed using the input data, the first key data, and the output mask value. | 12-22-2011 |
| 20120069993 | CRYPTOGRAPHIC APPARATUS AND MEMORY SYSTEM - According to one embodiment, a cryptographic apparatus includes: cryptographic cores (“cores”), an assigning unit, a concatenating unit, and an output controlling unit. If a CTS flag thereof is on, each core encrypts using a symmetric key cipher algorithm utilizing CTS, while using a symmetric key. When an input of a CTS signal is received, the assigning unit assigns first input data to a predetermined core and turns on the CTS flag thereof. The concatenating unit generates concatenated data by concatenating operation data generated during encrypting the first input data, with second input data that is input immediately thereafter. The output controlling unit controls outputting the concatenated data to the predetermined core, outputting first encrypted data obtained by encrypting the concatenated data, and over outputting second encrypted data obtained by encrypting the first input data, and further turns off the predetermined core's CTS flag. | 03-22-2012 |
| 20120131078 | ARITHMETIC DEVICE - According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p. | 05-24-2012 |
| 20120230492 | ENCRYPTION DEVICE - According to an embodiment, an encryption device includes a symmetric-key operation unit; a division unit; an exclusive OR operation unit; a multiplication unit that performs multiplication on a Galois field; and a control unit that controls the above units. When the input data is divided into blocks, with the predetermined length, and the first mode of operation is designated on a (j−1)-th block, the control unit performs control such that the multiplication unit performs multiplication with a predetermined value based on the (j−1)-th block, performs control such that the exclusive OR operation unit sums a multiplication result and data of a j-th block, and performs control such that the exclusive OR operation unit sums an operation result of the exclusive OR operation unit and an operation result of the multiplication unit on the (j−1)-th block. | 09-13-2012 |
| 20120237035 | KEY SCHEDULING DEVICE AND KEY SCHEDULING METHOD - According to one embodiment, in a key scheduling device, a non-linear transformation unit non-linearly transforms at least one of partial keys resulting from dividing an expanded key. A first linear transformation unit includes first and second circuits. The second circuit linearly transforms the partial key by directly using a transformation result from the non-linear transformation unit. A first storage stores the partial key linearly transformed by the first linear transformation unit. A second linear transformation unit linearly transforms, inversely to the first linear transformation unit, each of partial keys other than the partial key linearly transformed by the second circuit out of the partial keys stored in the first storage, and outputs inversely transformed partial keys. A second storage stores one of inputs to the second circuit. An outputting unit connects the respective inversely transformed partial keys and the input stored in the second storage to be output as a second key. | 09-20-2012 |
