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Koh Yoshikawa

Koh Yoshikawa, Nagano JP

Patent application numberDescriptionPublished
20110073903SEMICONDUCTOR DEVICE - A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer filed limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof.03-31-2011

Patent applications by Koh Yoshikawa, Nagano JP

Koh Yoshikawa, Tokyo JP

Patent application numberDescriptionPublished
20110012195SEMICONDUCTOR DEVICE - Between a source electrode (01-20-2011

Koh Yoshikawa, Matsumoto City JP

Patent application numberDescriptionPublished
20090014754TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE - A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n01-15-2009
20090189181Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor - A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.07-30-2009
20090206398SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.08-20-2009
20090230500Semiconductor device - A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type is provided in the first semiconductor layer. A third semiconductor region of the first conductivity type is provided in the second semiconductor region. The temperature detecting element is provided in the third semiconductor region and is separated from the first semiconductor layer by a PN junction.09-17-2009
20090291520METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs. The method includes forming p-type well region in the surface portion of single-crystal semiconductor substrate of a main semiconductor device, mounting a single-crystal silicon diode above p-type well region with an insulator film interposed between diode and p-type well region for forming subsidiary semiconductor device, forming an insulator film on the main semiconductor device such that single-crystal silicon diode is covered with insulator film for fixing single-crystal silicon diode to single-crystal semiconductor substrate, and forming a metal film on the main semiconductor device for further forming a cathode side wiring on n-type cathode region in single-crystal silicon diode and an anode side wiring on p-type anode region in single-crystal silicon diode.11-26-2009
20090315070SEMICONDUCTOR DEVICE - A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff. The pattern of arrangement of the lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer is independent of the arrangement pattern of the gate electrode structure.12-24-2009
20100207162VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE - A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n08-19-2010
20110156210SEMICONDUCTOR DEVICE - A semiconductor device according to embodiments of the invention includes an n06-30-2011

Patent applications by Koh Yoshikawa, Matsumoto City JP

Koh Yoshikawa, Matsumoto JP

Patent application numberDescriptionPublished
20100038675POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n02-18-2010