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| 20090157938 | ELECTRONIC DEVICES USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing. The electronic device housing further includes a passive or active cooling mechanism such as a fan positioned to cool the circuitry during normal operation. In one example, the electronic device does not include a host processor and instead a host processor is in a separate electronic device that communicates with the graphics processing circuitry through the divided multi connector element differential bus connector. In another example, a CPU (or one or more CPUs) is also co-located on the circuit substrate with the circuitry to provide a type of parallel host processing capability with an external device. | 06-18-2009 |
| 20090274366 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 11-05-2009 |
| 20100013840 | Compositing in Multiple Video Processing Unit (VPU) Systems - Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels. | 01-21-2010 |
| 20100166055 | Face Detection System for Video Encoders - Embodiments include a codec for use in a videoconferencing or similar system includes a video encoder pipeline that has a pre-processor component that is optimized to detect faces and compress the facial video data in an optimum manner. The codec has a pre-processing step that analyzes each frame on a per macroblock basis to determine the mathematical activity level per block. The activity level calculation is used as a parameter to the bitrate control module of the encoder to control the quantization, and thus the fine grained quality of the output data. An object detection module (e.g., a face detector) is placed in the pre-processing step. The object detection data is then combined with the activity level and object detection certainty value through a combinatorial algorithm comprising a weighted average or normalized multiplication process. | 07-01-2010 |
| 20100188411 | Non-Graphics Use of Graphics Memory - Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc. | 07-29-2010 |
| 20120002873 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 01-05-2012 |
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| 20110252180 | MEMORY CONTROLLER MAPPING ON-THE-FLY - Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks | 10-13-2011 |
| 20110252200 | COHERENT MEMORY SCHEME FOR HETEROGENEOUS PROCESSORS - Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity. | 10-13-2011 |
