Kode
Kranthi Kode, Stanford, CA US
Patent application number | Description | Published |
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20120197711 | Ranking Vendors by Combining Quantitative and Qualitative Characteristics of Third-Party Advertising - A computer-implemented method for ranking vendors by combining quantitative and qualitative characteristics of a third-party ad. The claimed method commences by storing a third-party internet ad, the third-party internet ad for hosting within a server in a third-party network, then measuring a latency score of the third-party network. Then monitoring the user's behavior to measure or calculate a click-through rate (CTR) score of the third-party internet ad, and additionally processing a quality score of the third-party internet ad for use in combining the latency score, the CTR score, and the quality score to form a reputation score. The reputation score is calculated using a coefficient of correlation for the quality score, and a coefficient of correlation for the latency score and a coefficient of correlation of the CTR score. The highest possible weight is given to the quality score while retaining maximum sensitivity to changes in latency and/or CTR scores. | 08-02-2012 |
Kranthl Kode, Stanford, CA US
Patent application number | Description | Published |
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20130268348 | Systems and Methods for Scoring Internet Ads and Ranking Vendors - Computer-implemented systems and method are taught for scoring an internet ad and/or ranking a vendor based on a combination of quantitative and qualitative characteristics. | 10-10-2013 |
Mahesh Raghunath Kode, Maharashtra IN
Patent application number | Description | Published |
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20090155509 | Holographic Flexible Tube Laminate For Packaging and Method of Making the Same - A holographic flexible tube laminate for packaging and a method of making the same. A flexible laminate substrate applied with an adhesive layer has a metalised holographic embossed pattern transferred onto the adhesive layer. The holographic side of the laminate substrate is further optionally applied with corona treatment, printed and applied with a protective transparent material coating. The edges of the laminate substrate without the adhesive layer are lap joined by heat sealing to form the tube laminate. | 06-18-2009 |
Ushasree Kode, Fremont, CA US
Patent application number | Description | Published |
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20150339464 | Restricted accounts on a mobile platform - Systems and techniques are provided for restricted accounts on a mobile platform. A request to create a restricted account may be received. The restricted account may be a user account with a restriction. Credentials for the restricted account may be received. A restriction for the restricted account may be received. The restriction may include an access restriction or a lifetime restriction. An access restriction may prevent an application from accessing the restricted account and a lifetime restriction may limit the lifetime of the restricted account. The restricted account may be stored with the credentials and the restriction. A request may be received for a list of user accounts from an application. The restricted account may be determined to include an access restriction that prevents the application from accessing the restricted account. The list of user accounts may be sent to the application and without an identifier for the restricted account. | 11-26-2015 |
Venkata Kode, Hayward, CA US
Patent application number | Description | Published |
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20150330914 | Wafer Edge Detection and Inspection - Methods and systems for determining wafer inspection coordinates for fixed location(s) on a wafer are provided. One system includes an illumination subsystem configured to direct light to a spot on an edge of a wafer. The spot extends beyond the edge of the wafer. The system also includes a stage that rotates the wafer thereby causing the spot to be scanned over the edge of the wafer. The system also includes a detector configured to detect light from the spot while the spot is being scanned over the edge and to generate output responsive thereto. The system further includes a computer processor configured to determine wafer inspection coordinates of two or more locations on the edge of the wafer based on the output and to determine wafer inspection coordinates of fixed location(s) on the wafer based on the wafer inspection coordinates of the two or more locations on the edge. | 11-19-2015 |