Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Kocon
Christopher B. Kocon, Mountaintop, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20090008706 | Power Semiconductor Devices with Shield and Gate Contacts and Methods of Manufacture - A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shape of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly. The first opening is filled with a conductive material that makes electrical contact with the lower shield poly and the second opening is filled with conductive material that makes electrical contact with the upper gate poly. The lower shield poly is electrically insulated from the substrate. The second oxide layer can be directly over the upper gate poly, the upper gate poly can be directly over the first oxide layer, the first oxide layer can be directly over the lower shield poly, and the first opening can be lower than the second opening. The device can further include a perimeter trench with extensions in the longitudinal direction that are staggered with respect to the active trenches so that there can be offset between the extensions of the perimeter trench and the active trenches. | 01-08-2009 |
| 20100171543 | PACKAGED POWER SWITCHING DEVICE - A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof. | 07-08-2010 |
| 20110163732 | Synchronous buck converter using shielded gate field effect transistors - A synchronous buck converter includes a high-side switch and a low-side switch serially coupled to one another. The low-side switch includes a field effect transistor that comprises: a trench extending into a drift region of the field effect transistor; a shield electrode in a lower portion of the trench, wherein the shield electrode is insulated from the drift region by a shield dielectric; a gate electrode in the trench over the shield electrode, wherein the gate electrode is insulated from the shield electrode by an inter-electrode dielectric; source regions adjacent the trench; a source metal contacting the source regions; and a resistive element having one end contacting the shield electrode and another end contacting the source metal in the field effect transistor. | 07-07-2011 |
Christopher B. Kocon, Plains, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20080197407 | Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture - A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer. | 08-21-2008 |
| 20080199997 | Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 08-21-2008 |
| 20100084706 | Power Semiconductor Devices and Methods of Manufacture - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 04-08-2010 |
Christopher B. Kocon, Mountain Top, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20110148506 | INTEGRATION OF MOSFETS IN A SOURCE-DOWN CONFIGURATION - An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch. | 06-23-2011 |
Waldemar Walter Kocon, Newburgh, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100038777 | METHOD OF MAKING A SIDEWALL-PROTECTED METALLIC PILLAR ON A SEMICONDUCTOR SUBSTRATE - A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon. | 02-18-2010 |