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| 20120120285 | METHOD AND APPARATUS FOR RECONFIGURING TIME OF FLIGHT SHOT MODE - A method and apparatus for configuring Time Of Flight sensor and data transfer for dynamically reconfigurable sensor mode change depending on scene characteristics. The method includes configuring the sensor configuration set on normal shot mode, performing scene analysis on at least one captured scenes, when dynamic motion is detected and the automatic shot mode sensor change is enabled, configuring the sensor to fast shot mode, and when in normal shot mode, capturing and transferring the full size TOF raw pixels for each phase, and when in fast shot mode, capturing and transferring less than all the size of the Time Of Flight raw pixels for each phase. | 05-17-2012 |
| 20120121165 | Method and apparatus for time of flight sensor 2-dimensional and 3-dimensional map generation - A method and apparatus for Time Of Flight sensor 2-dimensional and 3-dimensional map generation. The method includes retrieving Time Of Flight sensor fixed point data to obtain four phases of Time Of Flight fixed point raw data, computing Gray scale image array and phase differential signal arrays utilizing four phases of TOF fixed point raw data, computing Gray image array and Amplitude image array for fixed point, converting the phase differential signal array from fixed point to floating point, performing the floating point division for computing Arctan, TOF depthmap, and 3-dimensional point cloud map for Q format fixed point, and generating depthmap, 3-dimensional cloud coefficients and 3-dimensional point cloud for Q format fixed point. | 05-17-2012 |
| 20120121166 | METHOD AND APPARATUS FOR THREE DIMENSIONAL PARALLEL OBJECT SEGMENTATION - A method and apparatus for parallel object segmentation. The method includes retrieving at least a portion of a 3-dimensional point cloud data x, y, z of a frame, dividing the frame into sub-image frames if the sub-frame based object segmentation is enabled,
| 05-17-2012 |
| 20120123718 | METHOD AND APPARATUS FOR CONTROLLING TIME OF FLIGHT CONFIDENCE MAP BASED DEPTH NOISE AND DEPTH COVERAGE RANGE - A method and apparatus for fixing a depth map wrap-around error and a depth map coverage by a confidence map. The method includes dynamically determining a threshold for the confidence map threshold based on an ambient light environment, wherein the threshold is reconfigurable depending on LED light strength distribution in TOF sensor, extracting, via the digital processor, four phases of Time Of Flight raw data from the Time Of Flight sensor data, computing a phase differential signal array for fixed point utilizing the four phases of the Time Of Flight raw data, computing the depth map, confidence map and the average light signal strength utilizing the phase differential signal array, obtaining the dynamic confidence map threshold for wrap around error correction utilizing the average light signal strength, and correcting the depth map wrap-around error utilizing the depth map, the confidence map and the dynamic confidence map threshold. | 05-17-2012 |
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| 20090275266 | OPTICAL DEVICE POLISHING - Embodiments described herein provide methods for manufacturing an optical device having shaped sidewalls. A substrate material can be shaped to form a substrate portion of an optical device comprising an exit face and sidewalls positioned and shaped to reflect light to the exit face to allow light to escape the exit face. The sidewalls can be polished to a desired degree of polish. Polishing can be done using a polishing tool, etching, particle jet polishing or other polishing method. | 11-05-2009 |
| 20100066941 | HYBRID LIGHTING PANEL AND LCD SYSTEM - A hybrid lighting panel may have a first light guide and a second light guide proximate to the first light guide. The first light guide may receive light from a light source such as an LED array. The first light guide is configured to distribute the light along the length of the first light guide and distribute the light out a first light guide face such that light exiting the first light guide face enters the second light guide. The second light guide is configured to distribute light across the width of the second light guide and distribute light out a second light guide face. Hybrid lighting panels may be used individually or assembled as a system to provide light. A controller can control lighting to each panel to allow for individual dimming. One or more panels may be used to backlight an LCD layer. | 03-18-2010 |
| 20110032729 | ORTHOGONALLY SEPARABLE LIGHT BAR - Embodiments described herein provide optical systems in which phosphors are used to down-convert light. In general, optical systems can include a light guide configured to propagate light from an entrance face to a distal end along a propagation axis using total internal reflection. A phosphor layer can be disposed orthogonal to the entrance surface of the light guide. | 02-10-2011 |
| 20110044022 | SYSTEM AND METHOD FOR A PHOSPHOR COATED LENS - Embodiments disclosed herein provide optical systems utilizing photon conversion materials in conjunction with a light source and an LED. An LED can be positioned in a cavity defined by a base and one or more sidewalls. Phosphors can be disposed on the entrance face of a lens between the entrance face to the lens body and the LED so that light emitted from the LED will be incident on the phosphor and down converted before entering the lens body through the entrance face. The lens can positioned so that the phosphors are separated from the LED by a gap. | 02-24-2011 |
| 20110209825 | Method for Protecting Optical Devices During Manufacture - This disclosure regards methods for protecting a die during shaping and polishing of optical devices. According to various embodiments, layers can be added and removed from a wafer to protect both sides of the wafer during various steps of a manufacturing process. | 09-01-2011 |
| 20120068615 | System and Method for Color Mixing Lens Array - Embodiments described herein provide optical systems that can mix colors to produce illumination patterns having a large area with uniform color. One embodiment of an optical system can include a set of optical units that each produces an illumination pattern with uniform color and intensity. The optical units are spaced so that the individual illumination patterns overlap to create an overall illumination pattern with an overlap area. In the overlap area, the colors emitted by the individual optical units mix to create a desired color. Embodiments of optical systems can provide beam control so that the optical units emit a high percentage of light in beam. | 03-22-2012 |
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| 20080307240 | POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit including a power managed circuit ( | 12-11-2008 |
| 20090039952 | System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 02-12-2009 |
| 20090267638 | Apparatus, System and Method of Power State Control - An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch. | 10-29-2009 |
| 20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20110216619 | MEMORY POWER MANAGEMENT SYSTEMS AND METHODS - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 09-08-2011 |
