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Ko, Seongnam-Si
Byung-Hun Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120080601 | APPARATUS AND METHOD FOR DETECTING RADIATION - An apparatus and method for detecting radiation, which can improve the resolution of a radiation image and contribute to the simplification of the manufacture of the apparatus, are provided. The apparatus includes an upper electrode layer transmitting radiation; a first photoconductive layer becoming photoconductive upon exposure to the radiation and thus generating charges therein; a charge trapping layer trapping therein the charges generated in the first photoconductive layer; a second photoconductive layer becoming photoconductive upon exposure to rear light for reading out a radiation image; a lower transparent electrode layer charged with the charges trapped in the charge trapping layer; a micro lens layer disposed between the lower transparent electrode layer and a rear light emission unit and including a plurality of micro lenses respectively corresponding to a plurality of pixels; and the rear light emission unit applying the rear light to the second photoconductive layer via the micro lens layer and the lower transparent electrode layer in units of the pixels. | 04-05-2012 |
| 20120080603 | APPARATUS AND METHOD FOR DETECTING RADIATION - An apparatus and method for detecting radiation, which can improve the resolution of a radiation image and contribute to the simplification of the manufacture of the apparatus, are provided. The apparatus includes an upper electrode layer transmitting radiation; a first photoconductive layer becoming photoconductive upon exposure to the radiation and thus generating charges therein; a charge trapping layer trapping therein the charges generated in the first photoconductive layer and serving as a floating electrode; a second photoconductive layer becoming photoconductive upon exposure to rear light for reading out a radiation image; a lower transparent electrode layer charged with the charges trapped in the charge trapping layer; a rear light emission unit applying the rear light to the second photoconductive layer via the lower transparent electrode layer in units of pixels; and a data processing unit reading out a signal corresponding to the charges trapped in the charge trapping layer from the lower transparent electrode layer and generating a radiation image based on the read-out signal. | 04-05-2012 |
| 20120080604 | APPARATUS AND METHOD FOR DETECTING RADIATION - An apparatus and method for detecting radiation are provided. The apparatus includes an upper electrode layer transmitting radiation; a first insulating layer blocking charges from the upper electrode layer; a photoconductive layer becoming photoconductive upon exposure to the radiation; a second insulating layer protecting the photoconductive layer from a plasma discharge; a lower substrate facing the second insulating layer; a plurality of barrier ribs defining a cell structure between the second insulating layer and the lower substrate; a gas layer included in an inner chamber inside the cell structure and generating a plasma discharge; a bottom electrode formed on the lower substrate; a first radio frequency (RF) electrode formed over the bottom electrode and connected to a ground source; a second RF electrode to which RF power for generating plasma is applied; and a third insulating layer surrounding the first and second RF electrodes and thus insulating the first and second RF electrodes from the gas layer and the bottom electrode. | 04-05-2012 |
Chang Sup Ko, Seongnam-Si KE
| Patent application number | Description | Published |
|---|---|---|
| 20100235910 | SYSTEMS AND METHODS FOR DETECTING FALSE CODE - Systems and methods for detecting false code in web pages linked to a web site are provided. One system includes a web server for administering the web site and a surveillance server for collecting generated or updated web pages from among the web pages linked to the web site, selecting tags of a given tag type included in the collected web pages, determining whether the selected tags comprise false code, and providing the determination result to an administrator terminal such that an administrator can check the determination result. One method includes collecting web pages that were generated or updated within a set time period from among the web pages linked to the web site, determining whether tags included in the collected web pages comprise false code, and providing the determination result to an administrator terminal such that an administrator can check the determination result. | 09-16-2010 |
Chang Sup Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100235917 | SYSTEM AND METHOD FOR DETECTING SERVER VULNERABILITY - Systems and methods for detecting vulnerability of a server are provided. One system includes: a check server for collecting response information with respect to at least one predetermined command from one or more service servers that provide service, and thus may be attacked from outside, and detecting and analyzing vulnerabilities of the service servers based on the collected response information; an administration terminal for displaying the results of detecting and analyzing the vulnerabilities of the service servers; and a database for storing and managing pattern information concerning the detected vulnerabilities. One method includes identifying a server that may be attacked by port scanning, receiving response information with respect to at least one predetermined command from the identified server, detecting and analyzing vulnerability of the server based on the response information, and reporting the result of the detection to an administration terminal. | 09-16-2010 |
Choul Joo Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090273032 | LDMOS Device and Method for Manufacturing the Same - Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate. | 11-05-2009 |
| 20100140703 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring. | 06-10-2010 |
| 20100163990 | Lateral Double Diffused Metal Oxide Semiconductor Device - Disclosed is a lateral double diffused metal oxide semiconductor (LDMOS) device and methods of making the same. The LDMOS device may include a semiconductor substrate comprising a buried region and a first well region, a gate on the semiconductor substrate, a body region in the first well region and a source region in the body region on one side of the gate, a drift region and a drain region in the drift region on an opposite side of the gate relative to the body region, a second well region, a first deep sink region and a third well region in the first well region, and a second deep sink region in the first well region. | 07-01-2010 |
| 20100314675 | Power Semiconductor Device and Method for Manufacturing the Same - Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which may be formed in the process of forming the upper electrode of the PIP capacitor, so it is possible to realize an LDMOS having a higher breakdown voltage and lower Ron and Rsp without additional processing. A drain voltage, which may be different from a voltage applied to the first gate electrode, may be applied to the third gate electrode, so it is possible to realize an LDMOS having a high breakdown voltage and low Ron and Rsp. | 12-16-2010 |
Ho Jin Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100319125 | Heating and Sterilizing Apparatus for Bed Mattress - Provided is a heating and sterilizing apparatus. The heating and sterilizing apparatus for a bed mattress having a surface sheet constituting a top surface, a built-in elastic member for elastically supporting the surface sheet, and walls forming a front surface, a rear surface, and both side surfaces includes a mattress body providing a inner space, the mattress body having an installation hole, in which a portion of either side surface thereof is cut, a partition disposed inside the mattress body to partition the inner space defined inside the mattress body, a case disposed on the installation hole defined in the mattress body, and a heating and sterilizing part disposed in the case to heat and sterilize the inner space of the mattress body partitioned by the partition and calculate air within the inner space of the mattress body. | 12-23-2010 |
Hyun Soo Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090067531 | METHOD FOR REPORTING CHANNEL INFORMATION IN MULTIPLE ANTENNA SYSTEM - There is provided a method of reporting downlink channel information to a base station in a multiple antenna system. The method includes reporting a single rank for overall subband, the overall subband comprising a plurality of subbands and reporting a CQI for the single rank for at least one subband. Radio resources required for reporting channel information can be reduced and signaling overheads can be minimized. | 03-12-2009 |
Jong Sung Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090100747 | Fuel composition for internal-combustion engines containing trialkylamine - Disclosed herein is a fuel composition for internal combustion engines comprising a trialkylamine. Specifically, the fuel composition for internal combustion engines is prepared by adding a tertiary amine of trialkylamine to a gasohol which is a mixture of anhydrous or hydrous ethanol and naphtha, wherein the hydrous ethanol contains up to 10% by volume of water and shows an improved inhibition of a phase separation and corrosion. | 04-23-2009 |
Ju-Hyun Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080224191 | Image pickup device with prevention of leakage current - An image pickup device includes an active pixel sensor (APS), a row driver, and a leakage current breaker. The active pixel sensor includes an array of a plurality of pixels. The row driver selects at least one pixel to be activated to output signals. The leakage current breaker decreases the leakage current through the unselected pixels by applying a leakage current breaker voltage at the bit lines of the APS array. | 09-18-2008 |
| 20090174799 | Method of driving an image sensor - For driving an image sensor having a pixel with a transfer gate formed between a photo-detector and a floating diffusion region, a noise-reducing voltage is applied on the transfer gate during a first period of an integration mode. A blooming current voltage is applied on the transfer gate during a second period of the integration mode. A read voltage is applied on the transfer gate during a read mode after the integration mode. The read voltage has a higher magnitude than the blooming current voltage. With application of the noise-reducing voltage, noise is reduced and a dynamic range is extended for the image sensor. | 07-09-2009 |
Kuk-Won Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090251708 | FAST THREE-DIMENSIONAL SHAPE MEASURING APPARATUS AND METHOD - Disclosed herein is an apparatus for measuring the shape of a 3D object using an interferometer. The apparatus includes a light source unit, a beam splitter, a reference mirror, an actuator, an image pickup device, and a control unit. The light source unit emits light. The beam splitter divides the light from the light source unit. The reference mirror reflects light as a reference beam. The actuator moves the reference mirror. The image pickup device acquires a plurality of interference patterns by causing the reflected beam and the reference beam to interfere with each other. The control unit measures the shape of the object from the acquired interference patterns, outputs reference mirror drive signals to the actuator, and issues an image capture command at the end of image capture time that is shorter than settling time. | 10-08-2009 |
| 20090268212 | MOIRE SHAPE MEASUREMENT APPARATUS USING LIQUID CRYSTAL DISPLAY PANEL - Disclosed herein is a moiré shape measurement apparatus using a Liquid Crystal Display (LCD) panel. The moiré shape measurement apparatus includes a light source, a variable grating, a viewing lens, a light receiving unit, a computation unit, and a driving device. The light source emits light. The variable grating passes the emitted light therethrough, and creates a projection grating pattern. The viewing lens focuses a reflected grating pattern that is obtained when the projection grating pattern is reflected from the object. The light receiving unit receives the light of the reflected grating pattern passed through the viewing lens. The computation unit previously stores the viewing grating pattern, forms the moiré pattern by overlaying the reflected grating pattern, received from the light receiving unit, on the stored viewing grating pattern, and computes the shape of the object using the moiré pattern. The driving device adjusts a direction and a pitch in order to form a grating of the variable grating. | 10-29-2009 |
| 20090278965 | HIGH-SPEED PHOTOGRAPHING APPARATUS USING PLURAL CAMERAS - Disclosed herein is a high-speed photographing apparatus comprising a first camera for acquiring an image of an object, a second camera for acquiring the same image as the image acquired by the first camera, reflection means for reflecting the image of the object so that the first camera and the second camera obtain the same image with respect to the object, a controller for alternately providing a photographing signal to the first camera and the second camera at a speed higher than intrinsic photographing speeds of the first camera and the second camera such that the first camera and the second camera alternately capture images of the object, and an image synthesis section for synthesizing the alternately captured images. | 11-12-2009 |
| 20090279102 | METHOD AND APPARATUS FOR ACQUIRING REFERENCE GRATING OF THREE-DIMENSIONAL MEASUREMENT SYSTEM USING MOIRE - Disclosed herein is a method of acquiring a reference grating of a three-dimensional measurement system using moiré, wherein the three-dimensional measurement system includes a light source, a projection grating, a grating actuator and a camera, and analyzes the moiré pattern acquired through the camera to measure the shape of the object. The method includes the steps of acquiring an initial reference grating using the light source and the projection grating, confirming whether or not the acquired initial reference grating includes noise through a noise detector, and moving the projection grating through the grating actuator to acquire the next reference grating when the initial reference grating does not include noise and correcting the reference grating when the reference grating includes noise. The method can remove the noise included in the reference grating to improve the accuracy of measurement of an object. | 11-12-2009 |
Seung Han Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100077113 | DATA COMMUNICATION SYSTEM AND METHOD - Provided is a data communication system including a first-in first-out (FIFO) buffer having a fixed size; a central processing unit (CPU) that writes data stored in a memory into the FIFO buffer; a modem that reads the data written by the CPU from the FIFO buffer; and a modem controller that is connected to the FIFO buffer, the CPU, and the modem, respectively, and controls the CPU such that data having a larger volume than the size of the FIFO buffer can be processed. | 03-25-2010 |
Se-Whan Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090193408 | INTERFACE AND METHOD FOR INTERFACING ELEMENT MANAGEMENT SERVER IN WIRELESS TELECOMMUNICATION SYSTEM - Disclosed is an interface for interfacing an element management server in a wireless telecommunication system and a method for the same. The element management server for managing an ACR and an RAS, which are elements of the wireless telecommunication system, are adapted to interwork with the ACR and the RAS, respectively, so that the server can directly manage the ACR and the RAS and, particularly, the RAS can be operated more efficiently and maintained/repaired more quickly. The element management server manages the version of a package regarding all processors of lower elements and software to be loaded, and respective processors of the lower elements store nothing but their setup information (e.g. software, version) so that, if necessary, the element management server can transmit specific software only to the lower elements. This guarantees fast software download and provides users with stable services. | 07-30-2009 |
Tai-Young Ko, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110182099 | SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE - A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines. | 07-28-2011 |
| 20110199808 | MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED - A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block. | 08-18-2011 |
| 20110216616 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first and second memory cell array region, a first and second sense amplifier region interposed between the first and second memory cell array regions, a first column selection region interposed between the first sense amplifier region and the first memory cell array region and including a first column selection transistor connected between a first bit line and a first local data input/output (I/O) line, and a second column selection region interposed between the second sense amplifier region and the second memory cell array region and including a second column selection transistor connected between a second bit line and a second local data I/O line. A load of the second bit line is larger than a load of the first bit line and a threshold voltage of the first column selection transistor is higher than a threshold voltage of the second column selection transistor. | 09-08-2011 |