Patent application number | Description | Published |
20120212866 | OUTPUT DRIVER - An output driver having a power supply line, a control switch, at least one protection device and at least one voltage clamp device. The control switch disposed between the at least one protection device and the power supply line an output line. The at least one protection device disposed in a series arrangement between the output line and the control switch. The at least one voltage clamp device disposed across a corresponding protection device and adapted to clamp a voltage across the protection device below a predetermined threshold voltage. | 08-23-2012 |
20120229198 | POWER SUPPLY REGULATOR - Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply. | 09-13-2012 |
20130185688 | OVER STRESS VERIFY DESIGN RULE CHECK - Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured. | 07-18-2013 |
20140091837 | START-UP CIRCUIT FOR AN OUTPUT DRIVER - One or more techniques and systems for starting an output driver and an associated start-up circuit are provided herein. In some embodiments, a voltage provider is configured to charge a charge store to a pre-turn-on voltage. In some embodiments, an output driver is configured to control a connection between the charge store and the output driver. For example, the connection enables the charge store to discharge a voltage to the output driver, thus starting the output driver. Accordingly, a response time associated with starting the output driver is mitigated at least because the charge store is charged to the pre-turn-on voltage and connected to the output driver such that a gate of the driver is biased in a sudden fashion. In this manner, the driver is turned on more quickly. Additionally, effects associated with process, voltage, and temperature variations are mitigated, for example. | 04-03-2014 |
20150137875 | STACKED SEMICONDUCTOR ARRANGEMENT - Among other things, one or more stacked semiconductor arrangements or techniques for applying voltage schemes to such stacked semiconductor arrangements is provided. A stacked semiconductor arrangement comprises one or more tiers, such as a first tier comprising a first semiconductor structure, a second tier comprising a second semiconductor structure, or other tiers. A first voltage domain is applied to the first tier, such as a first substrate voltage of 0 v and a first power voltage of 1.6 v. A second voltage domain is applied to the second tier, such as a second substrate voltage of 1.6 v and a second power voltage of 3.3 v. In this way, semiconductor structures having different operational voltages are separated into different tiers, such as to mitigate damage to a lower voltage integrated circuit from a relatively higher voltage for a higher voltage integrated circuit. | 05-21-2015 |
Patent application number | Description | Published |
20120256293 | ONE-TIME PROGRAMMABLE DEVICES AND METHODS OF FORMING THE SAME - A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line. | 10-11-2012 |
20130092991 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE HAVING A CAPACITOR WELL DOPING DESIGN WITH IMPROVED COUPLING EFFICIENCY - The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode. | 04-18-2013 |
20140016399 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline. | 01-16-2014 |
20140124891 | FUSE DEVICE - A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line. | 05-08-2014 |
20140167118 | CROSSTALK IMPROVEMENT THROUGH P ON N STRUCTURE FOR IMAGE SENSOR - The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer. | 06-19-2014 |
20140346655 | MEMORY CELL - A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion. | 11-27-2014 |
20150016180 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate. | 01-15-2015 |
20150098266 | MECHANISMS FOR PREVENTING LEAKAGE CURRENTS IN MEMORY CELLS - Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation. | 04-09-2015 |
20150132905 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE HAVING A CAPACITOR WELL DOPING DESIGN WITH IMPROVED COUPLING EFFICIENCY - The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode. | 05-14-2015 |
Patent application number | Description | Published |
20110202690 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 08-18-2011 |
20110202780 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 08-18-2011 |
20120233388 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 09-13-2012 |
20120265905 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 10-18-2012 |
Patent application number | Description | Published |
20130121055 | WORD LINE DRIVER CELL LAYOUT FOR SRAM AND OTHER SEMICONDUCTOR DEVICES - A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power. | 05-16-2013 |
20140211574 | VOLTAGE DIVIDER CONTROL CIRCUIT - One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly. | 07-31-2014 |
20140233330 | WRITE ASSIST CIRCUIT, MEMORY DEVICE AND METHOD - A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell supply voltage node from the power supply voltage node in response to the write control signal having a second state. The bias voltage circuit generates, at an output thereof, an adjustable bias voltage lower than the power supply voltage. The second switch connects the cell supply voltage node to the output of the bias voltage circuit in response to the write control signal having the second state, and disconnects the cell supply voltage node from the output of the bias voltage circuit in response to the write control signal having the first state. | 08-21-2014 |
Patent application number | Description | Published |
20120267656 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light emitting device comprising: providing a substrate; forming an epitaxial stack on the substrate wherein the epitaxial stack comprising a first conductivity semiconductor layer, an active layer and a second conductivity semiconductor layer; forming a mesa on the epitaxial stack to expose partial of the first conductivity semiconductor layer; layer and etching the surface of the first conductivity semiconductor layer and forming a least one rough structure on the surface of the first conductivity semiconductor layer wherein the first conductivity semiconductor layer is sandwiched by the substrate and the active layer. | 10-25-2012 |
20130307002 | LIGHT EMITTING DEVICE WITH REFLECTIVE ELECTRODE - A light-emitting device comprises a semiconductor light emitting stack and an electrode on the semiconductor light emitting stack, wherein the electrode comprises a mirror layer, an adhesion layer inserted between the mirror layer and the semiconductor light emitting stack, a bonding layer, and a barrier layer inserted between the mirror layer and the bonding layer and covers the mirror layer to prevent the mirror layer reacting with the bonding layer, wherein the barrier layer comprises a first pair of different metals. | 11-21-2013 |
20140048830 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light-emitting device comprising steps of: providing a substrate, an active layer, and a first semiconductor layer between the substrate and the active layer; removing part of the active layer; and forming a rough structure in the first semiconductor layer while keeping the active layer attached to the substrate. | 02-20-2014 |
20140093991 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 04-03-2014 |
Patent application number | Description | Published |
20130093692 | GESTURE DETECTING METHOD CAPABLE OF FILTERING PANEL MISTOUCH - A gesture detecting method capable of filtering a panel mistouch includes following steps is provided. First, an area of a touch region for a touch event on a touch panel is detected. Next, it is determined whether the area of the touch region is greater than a minimum predetermined area value and smaller than a maximum predetermined area value. When a result of the above determination is affirmative, whether a shape of the touch area is a mistouch shape is determined. Finally, when the shape of the touch region is the mistouch shape, a set of touch coordinates is not reported. | 04-18-2013 |
20130257790 | CAPACITIVE TOUCH DEVICE AND SENSING METHOD THEREOF - A capacitive touch device includes a capacitive touch panel, a driving control unit, k ADCs, a multiplex network and a processing unit. The capacitive touch panel has an m×n sensing point matrix formed by m driving line and n sensing lines. The driving control unit is coupled to the m driving lines. The multiplex network connects the n sensing lines and the k ADCs by time-domain multiplexing. The processing unit is coupled to the k ADCs. At least a part of the driving lines and at least a part of the sensing lines are assigned to be electrically connected. The processing unit senses according to multiple frequencies to obtain multiple signal strength values, and selects the frequency corresponding to a smallest signal value to be a sensing frequency of the capacitive touch device. | 10-03-2013 |
20140015793 | CAPACITIVE TOUCH DEVICE AND DETECTION METHOD THEREOF - A detection method for a capacitive touch device is provided. The detection method includes steps of: driving an M | 01-16-2014 |
Patent application number | Description | Published |
20090046783 | Method and Related Device for Decoding Video Streams - A method for decoding a picture of a video stream includes decoding the video stream by a video decoder for generating a plurality of macroblocks corresponding to the picture, macroblock information corresponding to the plurality of macroblocks, and picture information corresponding to the picture; storing the macroblock information and the picture information into a memory buffer; and determining whether the picture is needed to be performed a de-blocking process by the video decoder according to the macroblock information and the picture information stored in the memory buffer. | 02-19-2009 |
20090060361 | METHOD FOR PROCESSING A MACRO BLOCK OF IMAGE DATA - The image data are coded with field DCT or frame DCT depending on the characteristics of the image data. However different coding types will result in different boundary marks of boundaries between adjacent blocks or adjacent macro blocks. Therefore the de-blocking of a boundary between two adjacent blocks or adjacent macro blocks should be performed according to the format of image data and the coding type of the adjacent blocks or adjacent macro blocks. | 03-05-2009 |
20090080517 | Method and Related Device for Reducing Blocking Artifacts in Video Streams - A method for reducing blocking artifacts in a video stream comprises receiving a picture of the video stream, wherein the picture includes a plurality of macroblocks and each of the plurality of macroblock includes four blocks, determining blocks with quantization parameters greater than a first threshold value in the picture, checking if block boundaries of the blocks are sharp and are real edges of objects in the picture according to pixel value differences between two adjacent pixels respectively located at both sides of the block boundaries, selecting filtering strengths of a de-blocking operation according to the pixel value differences when the block boundaries are sharp and are not real edges of the objects in the picture, and performing the de-blocking operation for two adjacent blocks at both sides of the block boundaries. | 03-26-2009 |