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| 20100142947 | APPARATUS AND METHOD FOR PSEUDO-INVERSE MULTIPLEXING/DE-MULTIPLEXING TRANSPORTING - A pseudo-inverse multiplexing/de-multiplexing apparatus and method are disclosed. The pseudo-inverse multiplexing apparatus maps a client signal to an OPUk-Xpv signal. The OPUk-Xpv signal has a payload area that can be segmented into a plurality of tributary slots and an overhead area into which frame configuration information related to the tributary slots is inserted. The pseudo-inverse multiplexing apparatus decides the number of tributary slots to be used to map client signals, according to a bit rate or bit tolerance of the client signals, and maps the client signals using the determined number of tributary slots. Accordingly, it is possible to map or frame a variety of client signals. | 06-10-2010 |
| 20100150163 | ETHERNET SWITCHING APPARATUS, AND METHOD FOR REDUCING POWER CONSUMPTION OF THE SAME - A method for reducing power consumption in an Ethernet switch is provided. The method includes: checking a state of packet data input through each of connection ports; detecting a connection port which has a packet rate lower than a predetermined reference value based on a result of the checking; and generating a data transfer control frame with respect to the connection port having the low packet rate and transmitting the generated data transfer control frame to an Ethernet apparatus connected to the corresponding connection port. Accordingly, a transmission line between the Ethernet switch and an Ethernet apparatus having the low to transmission rate is maintained in a low-power state, thereby reducing energy consumption in both Ethernet apparatuses. | 06-17-2010 |
| 20100158096 | EQUALIZATION APPARATUS AND METHOD OF COMPENSATING DISTORTED SIGNAL AND DATA RECEIVING APPARATUS - Provided are an equalization apparatus and method of compensating a distorted received signal. The equalization apparatus includes: a filter unit removing inter-symbol interference (ISI) from a multi-channel signal that is received; and a zero-offset controller identifying a zero offset of the multi-channel signal and determining operating coefficients of the filter unit by reflecting the identified zero offset. A response filter, which reduces loss and noise, can be used, and the structure of the response filter can be simplified. In addition, channel characteristics are estimated in real time at an initial stage of data transmission and reception. Thus, an equalizer optimized for channel interference characteristics can be provided. | 06-24-2010 |
| 20100158518 | MULTI-LANE SIGNAL TRANSMITTING AND RECEIVING APPARATUSES - An optical communication system is provided. In particular, multi-lane signal transmitting and receiving apparatuses capable of transmitting and receiving a multi-lane signal using the same inverse multiplexing scheme even when optic modules having several transport lane numbers are selected according to a purpose of use are provided. Each OTUk capable of containing a client signal in a transport hierarchy signal (OTUk-Xv) is defined as a virtual container, and Y virtual lanes are allocated to respective virtual containers X, in which identification information for the allocated virtual lanes is inserted into an overhead area and a transport hierarchy multi-lane signal is transmitted in the form of OTUk-XvYd. A receiving stage extracts the identification information inserted into the overhead area of the transport hierarchy signal in the form of OTUk-XvYd, compensates for a skew of the received signals, and aligns virtual lane signals for each virtual container to restore an OTUk-Xv signal that is an original transport hierarchy signal. | 06-24-2010 |
| 20100162033 | ETHERNET APPARATUS CAPABLE OF LANE FAULT RECOVERY AND METHODS FOR TRANSMITTING AND RECEIVING DATA - An Ethernet apparatus for performing lane fault recovery is provided. An Ethernet apparatus capable of lane fault recovery includes a data transmitter using a backup lane in the transport link to transmit data intended to be transmitted via the faulty lane when at least one faulty lane is detected from the data transfer lanes, and a data receiver recognizing the data received via the backup lane as data transferred via the faulty lane when the faulty lane is detected. In an Ethernet apparatus having a multi-lane structure, a lane fault and faulty lanes can be accurately recognized while maintaining compatibility with a standard Ethernet apparatus. | 06-24-2010 |
| 20100183301 | APPARATUS SUITABLE FOR TRANSPORTING CLIENT SIGNALS, AND APPARATUS AND METHOD SUITABLE FOR MAPPING OR DEMAPPING TRIBUTARY SLOTS FOR TRANSPORT OF CLIENT SIGNALS - Disclosed area method and apparatus of transporting client signals and a method and apparatus of mapping or demapping tributary slots for transport of client signals. The client signal transporting apparatus defines a bit rate of an optical transport signal, and bit-transparently maps and multiplexes client signals that operate at the defined bit rate. Also, the client signal transporting apparatus adjusts a bandwidth by extending a mapping area to increase a data capacity to be allocated to tributary slots. | 07-22-2010 |
| 20100223399 | METHOD AND APPARATUS FOR PROCESSING TIMESTAMP USING SIGNATURE INFORMATION ON PHYSICAL LAYER - A method and apparatus for processing a timestamp using signature information on a physical layer is provided. The timestamp processing terminal uses a pseudo-random binary sequence to assign signature information to a message which is to be sent to another terminal, and verifies the signature information on a physical layer. The signature information is used to identify the message as a sync message. Accordingly, it is possible to precisely process the timestamp. | 09-02-2010 |
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| 20100265274 | OFFSET COMPENSATION GAMMA BUFFER AND GRAY SCALE VOLTAGE GENERATION CIRCUIT USING THE SAME - Disclosed are an offset compensation gamma buffer and a gray scale voltage generation circuit using the same. The offset compensation gamma buffer includes: a buffer which outputs an input voltage input to a positive or negative input terminal as an output voltage; and a switching unit which selectively connects the input voltage and the output voltage of the buffer to the positive and negative input terminals in response to a control signal. The output voltage of the offset compensation gamma buffer is supplied to the input of a gray scale voltage generation circuit of a source driver for driving a liquid crystal panel. The offset of the offset compensation gamma buffer is compensated using an inversion timing of the control signal. The output voltage of the offset compensation gamma buffer is supplied as a reference voltage of the voltage divider unit for generating the gray scale voltages, and the offset of the gray scale voltages is also compensated. | 10-21-2010 |
| 20110012877 | METHOD FOR GENERATING FRAME-START PULSE SIGNALS INSIDE SOURCE DRIVER CHIP OF LCD DEVICE - Provided is a method of driving a liquid crystal display apparatus, and more particularly, to a method of generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip of a liquid crystal display apparatus. Accordingly, by generating a frame start pulse signal for instructing driving of a specific function of a source driver in a source driver chip unlike a conventional method where the frame start pulse signal is externally input, it is possible to reduce the number of input pins for inputting the frame start pulse signal and to remove an input line for inputting the frame start pulse signal in a process of mounting the source driver chip in a printed circuit board. | 01-20-2011 |
| 20110102687 | LCM FOR A DISPLAY PANEL - An LCM for a display panel includes a pixel array, a plurality of source driver ICs, and a plurality of gate driver ICs. The plurality of source driver ICs are disposed in a horizontal direction at an upper side or lower side of the pixel array. The plurality of gate driver ICs are disposed in a vertical direction at a left side or right side of the pixel array. The plurality of gate driver ICs are disposed at an opposite position to a position where a source driver IC, among the plurality of source driver ICs, first supplied with video data and a clock signal is disposed. | 05-05-2011 |
