| Patent application number | Description | Published |
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| 20080272818 | VOLTAGE-CONTROLLED OSCILLATOR GENERATING OUTPUT SIGNAL FINELY TUNABLE IN WIDE FREQUENCY RANGE AND VARIABLE DELAY CIRCUITS INCLUDED THEREIN - A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other. | 11-06-2008 |
| 20090051708 | ACTIVE DISPLAY DEVICE AND MIXING TYPE PIXEL DRIVING METHOD IN ACTIVE DISPLAY DEVICE - A mixing type pixel driving method in an active display device includes generating a digital data for a selected pixel, first driving the selected pixel to be illuminated with a first illumination intensity, and second driving the selected pixel to be illuminated with a second illumination intensity in a second illumination interval. A relative ratio of the second illumination intensity to the first illumination intensity is changed according to the value of the digital data. The number of the converted bits by DAC is reduced. Therefore, the less bit DAC is adaptable for the mixing type pixel driving method and the layout area and the consumption current can be decreased. | 02-26-2009 |
| 20090092212 | CLOCK EMBEDDED DIFFERENTIAL DATA RECEIVING SYSTEM FOR TERNARY LINES DIFFERENTIAL SIGNALING - A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal. | 04-09-2009 |
| Patent application number | Description | Published |
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| 20090026536 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A trench gate semiconductor device and a method for fabricating the same, which are capable of securing a sufficient margin for a photo process while achieving an enhancement in gate-source leakage characteristics, are disclosed. Embodiments relate to a method for fabricating a trench gate semiconductor device including forming a trench in an upper surface of an epitaxial layer formed over a semiconductor substrate. N type impurity ions may be implanted into a bottom surface of the trench, to form a diffusion layer. To form a well, P-type impurity ions may be implanted into a region beneath the diffusion layer. To form an oxide film buffer, the trench may be filled with an oxide. To form a gate trench, the resulting structure obtained after the filling of the oxide may be etched from the oxide film buffer to the epitaxial layer, in a region where a gate will be formed. NPN junctions may be formed beneath the oxide film buffer at opposite sides of the gate poly. Poly plugs may be formed to electrically connect P type portions of the NPN junctions to upper metal electrodes by filling the source trenches with polysilicon. The upper metal electrodes may be formed over the gate poly and over the poly plugs. | 01-29-2009 |
| 20090209073 | Gate Structure in a Trench Region of a Semiconductor Device and Method for Manufacturing the Same - Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively. | 08-20-2009 |
| 20090278205 | High Voltage BICMOS Device and Method for Manufacturing the Same - A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region. | 11-12-2009 |
| 20100025751 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film. | 02-04-2010 |
| 20100084700 | EEPROM and Method for Manufacturing EEPROM - An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer. | 04-08-2010 |
| 20100127321 | Semiconductor and Manufacturing Method for the Same - A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent to the gate pattern, having a shallower depth than a plurality of device isolation layers. | 05-27-2010 |
| 20100140699 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a logic device and a LDMOS device. The logic device including a first well of a first conductive type formed in the substrate, a first source region and a first drain region formed in the first well, and a first gate electrode formed over the first well. The LDMOS device including a deep well of the first conductive type formed in a second substrate, a body region of a second conductive type and a second well of a first conductive type formed in the deep well, a second source region formed in the body region, a second drain region formed in the second well, a second gate electrode formed over the second substrate, and an impurity layer of the first conductive type formed in the second substrate under the second gate electrode. | 06-10-2010 |
