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Knorr, US
Andreas Knorr, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090004865 | METHOD FOR TREATING A WAFER EDGE - A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer. | 01-01-2009 |
Andreas Knorr, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110045648 | METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION - Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon. | 02-24-2011 |
| 20110062501 | METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION - Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device. | 03-17-2011 |
| 20110068431 | SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES - Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HPDCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability. | 03-24-2011 |
| 20110163417 | METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE - A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. | 07-07-2011 |
Andreas Knorr, Wappinger Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100308382 | SEMICONDUCTOR STRUCTURES AND METHODS FOR REDUCING SILICON OXIDE UNDERCUTS IN A SEMICONDUCTOR SUBSTRATE - Methods are provided for fabricating semiconductor structures with an etch resistant layer that reduces undercuts in a silicon oxide layer of a semiconductor substrate. The semiconductor substrate is provided having the silicon oxide layer. The etch resistant layer is formed which uses at least a portion of the silicon oxide layer. A silicon-comprising material layer is formed overlying the etch resistant layer. The silicon-comprising material layer has an etch rate greater than an etch rate of the etch resistant layer when subjected to an etchant. The silicon-comprising material layer is etched with an etchant to form a fin structure on the silicon oxide layer. The etch resistant layer may be formed by ion implantation, diffusing nitrogen-supplying species into the silicon oxide layer, or forming an insulator material layer overlying the silicon oxide layer. | 12-09-2010 |
| 20100308440 | SEMICONDUCTOR STRUCTURES AND METHODS FOR STABILIZING SILICON-COMPRISING STRUCTURES ON A SILICON OXIDE LAYER OF A SEMICONDUCTOR SUBSTRATE - Methods are provided for substantially preventing and filling overetched regions in a silicon oxide layer of a semiconductor substrate. The overetched regions may be formed as a result of overetching of the silicon oxide layer during etching of an overlying silicon-comprising material layer to form a silicon-comprising structure. An etch resistant spacer may be formed after the initial or subsequent overetches. The etch resistant spacer may be formed by depositing an etch resistant material into the overetched region and etching the deposited etch resistant material to leave residual etch resistant material forming the etch resistant spacer. The etch resistant spacer may also be formed by exposing the silicon oxide layer in the overetched region to a nitrogen-supplying material to form a silicon oxynitride etch resistant spacer. | 12-09-2010 |
Andreas H. Knorr, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090289370 | LOW CONTACT RESISTANCE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Low contact resistance semiconductor devices and methods for fabricating such semiconductor devices are provided. In accordance with one exemplary embodiment, a method comprises depositing an insulating material overlying a metal silicide region and etching a contact opening within the insulating material and exposing the metal silicide region. The contact opening is at least partially bottom-filled with substantially pure cobalt. A conductor is deposited in the contact opening if, after the step of at least partially bottom-filling, the contact opening is not filled with the substantially pure cobalt. | 11-26-2009 |
| 20100320509 | Method for forming and integrating metal gate transistors having self-aligned contacts and related structure - According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate. | 12-23-2010 |
Charles T. Knorr, Akron, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20090051906 | Optical tracking device employing a three-axis gimbal - An optical tracking device, includes an azimuth sub-assembly providing a 360-degree range of motion and a transducer sensing the azimuth position within this range of motion; and an elevation sub-assembly coupled to the azimuth sub-assembly and providing at least a −30-degree to +100-degree range of motion and a transducer sensing the elevation position. A cross-elevation sub-assembly is coupled to the elevation sub-assembly and provides at least a ±14-degree optical range of motion and a transducer sensing the cross-elevation position. An elevation gyroscope is affixed to the elevation sub-assembly and generates an elevation rate signal; and a cross-elevation gyroscope is affixed to the elevation sub-assembly and generates a cross-elevation rate signal. A controller receives the azimuth, elevation, and cross-elevation position signals, and the elevation and cross-elevation rate signals and sends command signals to the sub-assemblies to initiate movement to allow inertially stabilized tracking of an object. | 02-26-2009 |
| 20090323203 | RISLEY INTEGRATED STEERING MODULE - A Risley integrated steering module is disclosed. The beam steering device consists of an outer assembly rotatable about an axis, and an inner assembly rotatable about the axis and positioned radially within the outer assembly. The beam steering device also includes a first prism connected to the outer assembly and a second prism connected to the inner assembly, and a stationary assembly, with the outer and inner assemblies being rotatable about the portion of the stationary assembly. In an alternative embodiment, the inner assembly rotates within the stationary assembly. The beam steering device also consists of beam expansion optics carried by either the inner assembly or the stationary assembly. | 12-31-2009 |
| 20110043880 | RISLEY INTEGRATED STEERING MODULE - A beam steering device is disclosed which includes an outer assembly rotatable about an axis by a motor assembly, and an inner assembly rotatable about the axis by another motor assembly and positioned radially within the outer assembly. The beam steering device also includes a first prism or grating connected to the outer assembly and a second prism or grating connected to the inner assembly. Both motor assemblies are axially displaced from the steering devices. The beam steering device also consists of beam expansion optics carried by either the inner assembly or the stationary assembly. In a further embodiment, an array of steerable sub-apertures are maintained within the inner and outer assemblies. | 02-24-2011 |
James Knorr, Tempe, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090306955 | METHOD AND SYSTEM FOR ANALYZING ROLLING ELEMENT BEARING SYSTEMS - Methods and systems for analyzing rolling element bearing systems are provided. A graphical user interface (GUI) is rendered on a display device. The graphical user interface includes a plurality of characteristics of the rolling element bearing system and a plurality of widgets associated with the characteristics. An indication of a value is received with each of the widgets. Each value is representative of the respective characteristic of the rolling element bearing system. A first analysis of the rolling element bearing system is performed based on the values with a first rolling element bearing solver. A second analysis of the rolling element bearing system is performed based on the values with a second rolling element bearing solver. Results of at least one of the first and second analyses are displayed on the display device. | 12-10-2009 |
Joseph R. Knorr, Edison, NJ US
| Patent application number | Description | Published |
|---|---|---|
| 20100212410 | METHOD OF MEASURING DEPOSITION ONTO A SUBSTRATE - A method of measuring the deposition of a composition onto a substrate. This information can be used to correlate how the composition will deposit on sanitary ware, such as shower cubicles, baths, and wash basins. The composition can be a liquid personal cleansing composition. | 08-26-2010 |
Lawrence Mark Knorr, Midlothia, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20090026137 | Liquid filtration media - A liquid filter with a composite medium that has a nanoweb adjacent to and optionally bonded to a microporous membrane. The membrane is characterized by an LRV value of 3.7 at a rated particle size, and the nanoweb has a fractional filtration efficiency of greater than 0.1 at the rated particle size of the membrane. The nanoweb also has a thickness efficiency ratio of greater than 0.0002 at that efficiency. The nanoweb acts to provide depth filtration to the membrane, prefilters particles and extends the lifetime of the membrane. | 01-29-2009 |
Lawrence Mark Knorr, Midlothian, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20080217239 | Liquid filtration media - A liquid filter with a composite medium that has a nanoweb adjacent to and optionally bonded to a microporous membrane. The membrane is characterized by an LRV value of 3.7 at a rated particle size, and the nanoweb has a fractional filtration efficiency of greater than 0.95 at the rated particle size of the membrane. The nanoweb also has a thickness efficiency ratio of greater than 0.01 at that efficiency. The nanoweb acts to provide depth filtration to the membrane, prefilters particles and extends the lifetime of the membrane. | 09-11-2008 |
| 20110042316 | LIQUID FILTRATION MEDIA - A liquid filter with a composite medium that has a nanoweb adjacent to and optionally bonded to a microporous membrane. The membrane is characterized by an LRV value of 3.7 at a rated particle size, and the nanoweb has a fractional filtration efficiency of greater than 0.1 at the rated particle size of the membrane. The nanoweb also has a thickness efficiency ratio of greater than 0.0002 at that efficiency. The nanoweb acts to provide depth filtration to the membrane, prefilters particles and extends the lifetime of the membrane. | 02-24-2011 |
Robert Ellsworth Knorr, Allentown, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20110083447 | APPARATUS AND METHOD FOR MONITORING AND REGULATING CRYOGENIC COOLING - An apparatus and method for monitoring and/or controlling cryogenic cooling by measuring the opacity of the vapor cloud ( | 04-14-2011 |
Robert J. Knorr, Maricopa, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080289515 | PEPPER DE-STEMMING - A way of dealing with challenges to the pepper processing industry and pepper growers is to mechanize pepper processing, including the de-stemming of whole peppers. The present example provides a method of or mechanically de-stemming whole peppers. The method provides for the recognition of a pepper's shoulder in order to generate a control signal to initiate a process to de-stem the pepper. In particular, several implementations of the method are provided that may include a mechanical system, a laser system, a machine vision system, a combination of a machine vision system and the laser system, and other equivalent implementations. Additionally disclosed, are methods of processing whole peppers utilizing automated de-stemming. | 11-27-2008 |
| 20090022865 | PEPPER BOAT MAKER - The present example provides an automated or mechanized, way of making a pepper boat from a de-stemmed pepper. In making the pepper boat, de-stemmed peppers may be split by a splitting assembly. As the pepper is split, or subsequently, a whisk assembly tends to clean a portion of the veins and seeds from the split pepper pod to form two substantially equal halves of a pepper boat, suitable for further food processing. | 01-22-2009 |