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Knips
Kristof Knips, Aachen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100077670 | CORNER PORTION FOR A HIDDEN FRAME WINDOW RUN, A SEALING GASKET FORMING THIS RUN AND A SEALING SYSTEM INCORPORATING IT - The present invention relates to a corner connecting portion for a sealing gasket of a motor vehicle window glass, the gasket forming a window glass run channel of the hidden frame type. It is designed to connect a top segment to an ascending segment of the glass run channel, and it comprises: an upper part comprising an upper face designed to be sealingly mounted under the vehicle bodywork and a lower face designed to be mounted on said pillar by mounting means, and a lower part which is connected to the upper part by forming a “⊂” designed to surround an outer end of said pillar and which is designed to be sealingly in contact with the window glass. The mounting means comprise a pin which is inserted into a corresponding through hole formed in the upper part so as to extend from the upper face to the lower face, the pin being pushed through a pillar opening in an assembly position, to minimize the displacements of the gasket in response to ageing and fatigue cycles due to slams of the door. | 04-01-2010 |
Thomas J. Knips, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090217112 | AC ABIST Diagnostic Method, Apparatus and Program Product - A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester. | 08-27-2009 |
Thomas J. Knips, Wappinger Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080263417 | Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy - Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief. | 10-23-2008 |