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Knickerbocker, NY
Glenn Stuart Knickerbocker, Kingston, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090319942 | Context Sensitive Paging - The invention addresses the need to view an entire document element, such as a photograph, paragraph, etc. when paging. A window generated by an application such as a browser includes a succession of document elements. The window has an actual top and an actual bottom. The computer system selects a paging step size automatically, wherein the paging step size is selected from a group. The group includes a first step size that is of a size such that paging downward by the first step size from the current window position advances the window to a location placing the top of the at least one document element a predetermined distance below the top of the window. | 12-24-2009 |
| 20100198664 | VARIABLE ROAD TOLL PREDICATED ON INSTANTANEOUS POINT-TO-POINT TRAFFIC VOLUME CALCULATION - A method, a system and a computer program product are directed towards determination of a variable toll for a particular target vehicle using a particular point-to-point travel segment of a particular toll road. The variable toll is calculated predicated upon a deviation of an instantaneous point-to-point traffic volume for the particular target vehicle exiting the toll road in comparison with an arbitrarily determined baseline point-to-point traffic volume. The instantaneous point-to-point traffic volume includes vehicles traveling at least a portion of the same point-to-point travel segment as the target vehicle during an effective time interval when the target vehicle traveled the point-to-point travel segment. | 08-05-2010 |
John Knickerbocker, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110290402 | Handler Attachment for Integrated Circuit Fabrication - A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive. | 12-01-2011 |
| 20110290406 | Laser Ablation for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler. | 12-01-2011 |
| 20110290413 | Laser Ablation of Adhesive for Integrated Circuit Fabrication - A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. | 12-01-2011 |
John Knickerbocker, Monroe, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080206960 | REWORKABLE CHIP STACK - A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point. | 08-28-2008 |
John U. Knickerbocker, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100276796 | REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD - An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts. | 11-04-2010 |
| 20110042795 | Three-Dimensional Silicon Interposer for Low Voltage Low Power Systems - Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections. | 02-24-2011 |
John U. Knickerbocker, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080231311 | PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY - A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts. | 09-25-2008 |
| 20090032962 | CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION - The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component. | 02-05-2009 |
John U. Knickerbocker, Yokrtown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110042820 | 3D SILICON-SILICON DIE STACK STRUCTURE AND METHOD FOR FINE PITCH INTERCONNECTION AND VERTICAL HEAT TRANSPORT - A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit. | 02-24-2011 |
John Ulrich Knickerbocker, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110019368 | Silicon Carrier Structure and Method of Forming Same - A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate. | 01-27-2011 |
Sarah H. Knickerbocker, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090020590 | PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGANO-TIN/TIN DEPOSITS ON THE WAFER SURFACE - A method is provided for making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin or other solder component from the solder onto the wafer surface which tin can cause shorts or other defects in the wafer. The method is particularly useful for well-known C4NP interconnect technology. In one aspect of the invention, a reducing gas flow rate is used to remove oxides from the solder surfaces and wafer pad surfaces and is of a sufficient determined or pre-determined flow and/or chamber or mold/wafer spacing to provide a gas velocity across the solder surfaces and wafer pad surfaces so that Sn or other contaminants do not deposit on the wafer surface during solder transfer. In another aspect, the transfer contact is performed below the melting point of the solder and subsequently heated to above the melting temperature while in transfer contact. The heated solder in contact with the wafer pads is transferred to the wafer pads. | 01-22-2009 |
| 20090163019 | FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING - A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter. | 06-25-2009 |
| 20110079702 | FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE LAYER - A method of forming a mold having a protective layer includes forming a mold substrate having at least one substantially planar surface, depositing a layer of mold protection material onto the at least one substantially planar surface, and etching a plurality of cavities into the at least one substantially planar surface through the mold protection layer. | 04-07-2011 |