Klumperink
Eric Klumperink, Lichtenvoorde NL
Patent application number | Description | Published |
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20120154003 | SPUR REDUCTION TECHNIQUE FOR SAMPLING PLL'S - Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced. | 06-21-2012 |
Eric Klumperink, Lichtenvourde NL
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20130038365 | Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time. | 02-14-2013 |
Eric A. M. Klumperink, Lichtenvoorde NL
Patent application number | Description | Published |
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20110298521 | POLYPHASE HARMONIC REJECTION MIXER - A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage ( | 12-08-2011 |