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Kleihorst, Kasterlee
Richard P. Kleihorst, Kasterlee BE
| Patent application number | Description | Published |
|---|---|---|
| 20080229063 | Processor Array with Separate Serial Module - A processor array has processor elements ( | 09-18-2008 |
| 20090119479 | INTEGRATED CIRCUIT ARRANGEMENT FOR CARRYING OUT BLOCK AND LINE BASED PROCESSING OF IMAGE DATA - An integrated circuit arrangement has a processor array ( | 05-07-2009 |
| 20100007491 | INTEGRATED IMAGE RECOGNITION AND SPECTRAL DETECTION DEVICE AND A DEVICE AND METHOD FOR AUTOMATICALLY CONTROLLING THE SETTINGS OF A LIGHT BY IMAGE RECOGNITION AND SPECTRAL DETECTION OF THE LIGHT - The invention relates to an integrated image recognition and spectral detection device particularly suitable for monitoring settings of a light. The invention also relates to automatically controlling the settings of a light by image recognition and spectral detection of the light, particularly to automatically controlling the color point of the light in response to the image recognition. The invention provides an integrated image recognition and spectral detection device ( | 01-14-2010 |
| 20100103258 | CAMERA ARRANGEMENT AND METHOD FOR DETERMINING A RELATIVE POSITION OF A FIRST CAMERA WITH RESPECT TO A SECOND CAMERA - A method for determining a relative position of a first camera with respect to a second camera, comprises the followings steps: | 04-29-2010 |
| 20100248831 | ACQUIRING IMAGES WITHIN A 3-DIMENSIONAL ROOM - The application relates to acquiring images within a 3-dimensional room | 09-30-2010 |
| 20110126073 | Error Correction in an Electronic Circuit - An electronic circuit has a data producing circuit ( | 05-26-2011 |
Richard Petrus Kleihorst, Kasterlee BE
| Patent application number | Description | Published |
|---|---|---|
| 20090046953 | Image Processing Apparatus And Method - An image processing apparatus ( | 02-19-2009 |
| 20100020178 | CALIBRATING A CAMERA SYSTEM - A method of calibrating a camera system which is capable of recording at least two images simultaneously is described. The method comprises the step of processing a first pair of images, wherein the processing step comprises transforming at least one of a first and a second image of the first pair through a projective map on a plane, the map depending on one or more parameter values, so as to align an epipolar line in the first image with a corresponding epipolar line in the second image of the first pair, resulting in a second pair of images. The method further comprises estimating respective values for a disparity, which values associate respective first pixels along a first epipolar line in a first image of the second pair with respective second pixels along a corresponding second epipolar line in a second image of the second pair, and displacing respective pixels of the first epipolar line in the first image of the second image pair in accordance with a respective value of the disparity for the respective pixels. The method further comprises determining a measure of error between the first and the second image of the second image pair, dependent on the one or more parameters, determining an update for the one or more parameter values for reducing a value of the measure of error, and updating the one or more parameter values, using the update. | 01-28-2010 |
| 20100283870 | FLASH LIGHT COMPENSATION SYSTEM FOR DIGITAL CAMERA SYSTEM - The invention refers to a flash light compensation system and corresponding method for digital camera systems, wherein a luminance compensation is carried out on an image of a scene ( | 11-11-2010 |
| 20110134131 | SIMD PARALLEL PROCESSOR ARCHITECTURE - A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means. | 06-09-2011 |