Patent application number | Description | Published |
20080251779 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-16-2008 |
20080283925 | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement - In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another. | 11-20-2008 |
20090085163 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 04-02-2009 |
20090101975 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD | 04-23-2009 |
20090121289 | FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE AND ASSOCIATED PRODUCTION METHOD - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1 -x),where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized. | 05-14-2009 |
20090309167 | Electronic Device and Manufacturing Method Thereof - Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions. | 12-17-2009 |
20100193867 | Silicided Semiconductor Structure and Method of Forming the Same - A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer. | 08-05-2010 |
20100252799 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-07-2010 |
20100252895 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-07-2010 |
20110031530 | FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized. | 02-10-2011 |
20110095347 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 04-28-2011 |
20120068149 | APPARATUS OF MEMORY ARRAY USING FINFETS - In one or more embodiments, a semiconductor device a FinFET device and a second device. In one or more embodiments, the semiconductor device has a contact element coupled between a surface of the fin and the second device. | 03-22-2012 |
20130009215 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 01-10-2013 |
20140077146 | SEMICONDUCTOR DEVICE INCLUDING FINFET DEVICE - A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 03-20-2014 |
20140124827 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor. | 05-08-2014 |
20140167215 | ELECTRONIC CIRCUIT ARRANGEMENT - An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias. | 06-19-2014 |