Patent application number | Description | Published |
20080251849 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device comprising a first semiconductor region and a second semiconductor region,
| 10-16-2008 |
20090014205 | PRINTED CIRCUIT BOARD ASSEMBLED PANEL, UNIT SHEET FOR PACKAGING A PRINTED CIRCUIT BOARD, RIGID-FLEXIBLE BOARD AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a printed circuit board assembled panel by a simple process with an excellent material yield and a high conforming product rate. Unit printed circuit boards previously manufactured are arranged in a frame in a prescribed relationship. Then, the printed circuit boards are fixed to one another, and the printed circuit board and the frame body are fixed to one another. | 01-15-2009 |
20090014795 | Substrate for field effect transistor, field effect transistor and method for production thereof - A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition. | 01-15-2009 |
20090134454 | Fin-type field effect transistor, semiconductor device and manufacturing process therefor - A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer. | 05-28-2009 |
20090321849 | SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness. | 12-31-2009 |
20100076741 | SYSTEM, METHOD AND PROGRAM FOR DETERMINING WORST CONDITION OF CIRCUIT OPERATION - A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition. | 03-25-2010 |
20100217568 | VARIATION SIMULATION SYSTEM, METHOD FOR DETERMINING VARIATIONS, APPARATUS FOR DETERMINING VARIATIONS AND PROGRAM - Disclosed is a variation simulation system including a variation analysis unit that acquires the results of statistical analysis of variations of characteristics of a plural number of target devices, a model analysis unit that acquires the results of analysis showing how the characteristics respond to variations of a parameter with respect to a model for simulation that simulates each target device, a fitting execution unit that collates the results obtained by the variation analysis unit to those obtained by the model analysis unit and determines the manner of variations of the parameter in order to reproduce the variations of each target device in accordance with the model, and a result output unit that outputs the information on the manner of variations of the parameter determined by the fitting execution unit. A transformation matrix is determined by multiplying a pseudo inverse matrix of a response matrix, a matrix made up of principal component vectors and an arbitrary unitary matrix. | 08-26-2010 |
20110018056 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor. | 01-27-2011 |
20110024828 | SEMICONDUCTOR STORAGE DEVICE - An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other. | 02-03-2011 |
20110059584 | MANUFACTURING PROCESS OF FIN-TYPE FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR - A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer. | 03-10-2011 |
20110061903 | Multilayered printed wiring board and method for manufacturing the same - A multilayered printed wiring board includes a flexible wiring board with wiring layers on both main surfaces thereof; a rigid wiring board with wiring layers on both main surfaces thereof and formed opposite to the flexible wiring board under the condition that an area of the main surface of the rigid wiring board is smaller than an area of the main surface of the flexible wiring board; and an electric/electronic component embedded in the rigid wiring board. | 03-17-2011 |
20130220686 | MULTILAYERED PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers. | 08-29-2013 |