Patent application number | Description | Published |
20100042806 | DETERMINING INDEX VALUES FOR BITS OF A BINARY VECTOR - In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M sub-vector index values, where each sub-vector index value corresponds to a different bit of a sub-vector of the binary vector. The masking technique is applied such that (i) the sub-vector index values that correspond to bits having a value of 0 are zeroed out and (ii) the sub-vector index values that correspond to the bits having a value of 1 are left unchanged. The masked sub-vector index values are sorted, and index values are calculated based on the masked sub-vector index values. The index values generated are then distributed uniformly to a number M of index memories such that the M index memories store substantially the same number of index values. | 02-18-2010 |
20100042890 | ERROR-FLOOR MITIGATION OF LDPC CODES USING TARGETED BIT ADJUSTMENTS - Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials. | 02-18-2010 |
20100042891 | ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 02-18-2010 |
20100042892 | RECONFIGURABLE TWO'S-COMPLEMENT AND SIGN-MAGNITUDE CONVERTER - In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above. The reconfigurable SMT2 is selectively configurable to operate in (i) a five-bit mode to convert two five-bit messages concurrently and (ii) a ten-bit mode to convert one ten-bit message at a time. | 02-18-2010 |
20100042893 | RECONFIGURABLE CYCLIC SHIFTER - In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message. | 02-18-2010 |
20100042894 | ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING LMAXB-BASED SELECTION OF ALTERNATIVE LAYERED-DECODING SCHEDULES - A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer L | 02-18-2010 |
20100042895 | SELECTING LAYERED-DECODING SCHEDULES FOR OFFLINE TESTING - A method for selecting a population of schedules of an n-layer decoder for offline schedule testing. The method identifies one or more triads, where a triad is a sequence of three layers where no layer is repeated. The method selects a set of schedules where each of the identified triads is contained in at least one schedule. The method associates each selected schedule with one or more key-layer values, where a key layer is the middle layer of a triad contained within the schedule. | 02-18-2010 |
20100042896 | ERROR-FLOOR MITIGATION OF LAYERED DECODERS USING NON-STANDARD LAYERED-DECODING SCHEDULES - A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer L | 02-18-2010 |
20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |
20100042898 | RECONFIGURABLE MINIMUM OPERATOR - In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first non-reconfigurable minimum operator determines whether a first half of a first ten-bit message is less than a first half of a second ten-bit message, and the second non-reconfigurable minimum operator determines whether a second half of the first ten-bit message is less than a second half of the second ten-bit message. The reconfigurable minimum operator determines whether the first ten-bit message is less than the second ten-bit message based on the comparisons of the first and second non-reconfigurable minimum operators. | 02-18-2010 |
20100042902 | ERROR-FLOOR MITIGATION OF ERROR-CORRECTION CODES BY CHANGING THE DECODER ALPHABET - In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased. | 02-18-2010 |
20100042903 | RECONFIGURABLE ADDER - In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums. | 02-18-2010 |
20100042904 | BREAKING UNKNOWN TRAPPING SETS USING A DATABASE OF KNOWN TRAPPING SETS - In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values. | 02-18-2010 |
20100042905 | ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder. | 02-18-2010 |
20100042906 | ADJUSTING SOFT-OUTPUT VALUES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword. | 02-18-2010 |
20100241921 | ERROR-CORRECTION DECODER EMPLOYING MULTIPLE CHECK-NODE ALGORITHMS - In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors. | 09-23-2010 |
20110029835 | Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding - Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix including selecting a non-affiliated variable node; identifying a check node of the lowest degree; connecting a first edge of the non-affiliated variable node to the identified check node; and connecting one or more additional edges of the non-affiliated variable node to check nodes in accordance with a quasi-cyclic constraint associated with a circulant is disclosed. | 02-03-2011 |
20110119056 | SUBWORDS CODING USING DIFFERENT INTERLEAVING SCHEMES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding interleavers/deinterleavers in the different subword-processing paths use different interleaving/deinterleaving algorithms. | 05-19-2011 |
20110119553 | SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices. | 05-19-2011 |
20110126075 | ROM LIST-DECODING OF NEAR CODEWORDS - Certain embodiments of the present invention are methods for the organization of trapping-set profiles in ROM and for the searching of those profiles during (LDPC) list decoding. Profiles are ranked by dominance, i.e., by their impact on the error-floor characteristics of a decoder. More-dominant trapping-set profiles contain information about both unsatisfied check nodes (USCs) and mis-satisfied check nodes (MSCs), while less-dominant trapping-set profiles contain information about only USCs. Trapping-set profile information is organized into a number of linked, hierarchical data tables which allow for the rapid location and retrieval of most-dominant matching trapping-set profiles using a pointer-chase search. | 05-26-2011 |
20110131462 | MATRIX-VECTOR MULTIPLICATION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector. | 06-02-2011 |
20110131463 | FORWARD SUBSTITUTION FOR ERROR-CORRECTION ENCODING AND THE LIKE - In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector. | 06-02-2011 |
20110138253 | RAM LIST-DECODING OF NEAR CODEWORDS - Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded correct codeword is compared to a near codeword to generate a new trapping-set profile, and the profile written to RAM. Record is kept of how many times RAM has been searched since a profile was last matched. Profiles that have not been matched within a specified number of searches are purge-eligible. Purge-eligible profiles are further ranked on other factors, e.g., number of times a profile has been matched since it was added, number of unsatisfied check nodes, number of erroneous bit nodes. If there is insufficient free space in RAM to store a newly-discovered profile, then purge-eligible profiles are deleted, beginning with the lowest-ranked profiles, until either (i) sufficient free space is created or (ii) there are no more purge-eligible profiles. | 06-09-2011 |
20110167246 | Systems and Methods for Data Detection Including Dynamic Scaling - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric. | 07-07-2011 |
20110264979 | ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 10-27-2011 |
20110264980 | Systems and Methods for Low Density Parity Check Data Decoding - Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight. | 10-27-2011 |
20110264987 | Systems and Methods for Low Density Parity Check Data Encoding - Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value. | 10-27-2011 |
20110320902 | CONDITIONAL SKIP-LAYER DECODING - In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder. | 12-29-2011 |
20120005551 | BREAKING TRAPPING SETS USING TARGETED BIT ADJUSTMENT - In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial. | 01-05-2012 |
20120005552 | ON-LINE DISCOVERY AND FILTERING OF TRAPPING SETS - A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system. | 01-05-2012 |
20120017132 | LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing. | 01-19-2012 |
20120030539 | ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION - Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing. | 02-02-2012 |
20120079340 | COMMUNICATIONS SYSTEM EMPLOYING LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING - In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path. | 03-29-2012 |
20120099670 | COMMUNICATIONS SYSTEM SUPPORTING MULTIPLE SECTOR SIZES - In one embodiment, a configurable communications system accommodates a plurality of different transmission word sizes. In a transmit path, the system inserts a number of padding bits corresponding to missing user-data bits onto the end of an input data sequence to generate a set of data having N bits. The N bits are interleaved and error-correction (EC) encoded to generate parity bits corresponding to an EC codeword. The parity bits are de-interleaved and multiplexed with the input data stream to generate a transmission word. In a receive path, a channel detector recovers channel values corresponding to the transmission word. Padding values, corresponding to the missing-bit locations, are inserted among the channel values. The resulting channel values are interleaved and EC decoded to recover the EC codeword. The data bits of the codeword are de-interleaved, and the padding bits corresponding to the missing channel values are discarded. | 04-26-2012 |
20120113984 | MULTI-STAGE INTERCONNECTION NETWORKS HAVING SMALLER MEMORY REQUIREMENTS - In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages. | 05-10-2012 |
20120117295 | MULTI-STAGE INTERCONNECTION NETWORKS HAVING FIXED MAPPINGS - In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages. | 05-10-2012 |
20130124590 | RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT - In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement. | 05-16-2013 |
20130246894 | DECODING METHOD AND APPARATUS FOR NON-BINARY, LOW-DENSITY, PARITY CHECK CODES - Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute d | 09-19-2013 |