Patent application number | Description | Published |
20110289332 | METHOD AND APPARATUS FOR POWER MANAGEMENT IN A MULTI-PROCESSOR SYSTEM - Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt. | 11-24-2011 |
20110296412 | APPROACHES FOR SECURING AN INTERNET ENDPOINT USING FINE-GRAINED OPERATING SYSTEM VIRTUALIZATION - Approaches for executing untrusted software on a client without compromising the client using micro-virtualization to execute untrusted software in isolated contexts. A template for instantiating a virtual machine on a client is identified in response to receiving a request to execute an application. After the template is identified, without human intervention, a virtual machine is instantiated, using the template, in which the application is to be executed. The template may be selected from a plurality of templates based on the nature of the request, as each template describe characteristics of a virtual machine suitable for a different type of activity. Selected resources such as files are displayed to the virtual machines according to user and organization policies and controls. When the client determines that the application has ceased to execute, the client ceases execution of the virtual machine without human intervention. | 12-01-2011 |
20120144215 | MAXIMUM CURRENT LIMITING METHOD AND APPARATUS - The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current. | 06-07-2012 |
20120144221 | LOAD STEP MITIGATION METHOD AND APPARATUS - A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation. | 06-07-2012 |
20120159123 | CSTATE BOOST METHOD AND APPARATUS - A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State. | 06-21-2012 |
20120159198 | PROCESSOR POWER LIMIT MANAGEMENT - A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target. | 06-21-2012 |
20120159224 | HARDWARE ASSISTED PERFORMANCE STATE MANAGEMENT BASED ON PROCESSOR STATE CHANGES - A processor is configured to support a plurality of performance states and idle states. The processor includes a first programmable location associated with a first idle state and configured to store first entry performance state (P-State) information. The first entry P-State information identifies a first entry P-State. The processor is configured to receive a request to enter the first idle state, retrieve the first entry P-State information and enter the first entry P-State. The processor may include a second programmable location associated with the first idle state and configured to store first exit P-State information. The first exit P-State information identifies a first exit P-State. The processor may be configured to receive a request to exit the first idle state, retrieve the first exit P-State information and enter the first exit P-State. | 06-21-2012 |
20130024829 | METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT - Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state. | 01-24-2013 |
20130055256 | APPROACHES FOR AUTOMATED MANAGEMENT OF VIRTUAL MACHINES FOR RUNNING UNTRUSTED CODE SAFELY - Approaches for transferring data to a client by safely receiving the data in or more virtual machines. In response to the client determining that digital content, originating from an external source, is to be received or processed by the client, the client identifies, without human intervention, one or more virtual machines, executing or to be executed on the client, into which the digital content is to be stored. In doing so, the client may consult policy data to determine a placement policy, a containment policy, and a persistence policy for any virtual machine to receive the digital content. In this way, digital content, such as executable code or interpreted data, of unknown trustworthiness may be safely received by the client without the possibility of any malicious code therein from affecting any undesirable consequence upon the client. | 02-28-2013 |
20130132691 | APPROACHES FOR EFFICIENT PHYSICAL TO VIRTUAL DISK CONVERSION - Approaches for providing a guest operating system to a virtual machine. A read-only copy of one or more disk volumes, including a boot volume, is created. A copy of a master boot record (MBR) for the one or more disk volumes is also stored. The read-only copy may be, but need not be, made using a Volume Shadow Copy Service (VSS). A virtual disk, for use by the virtual machine, is created based on the read-only copy of the one or more disk volumes and the copy of the master boot record (MBR), wherein the virtual disk comprises the guest operating system used by the virtual machine. In this way, a single installed operating system may provide both the host operating system and the guest operating system. | 05-23-2013 |
20140380315 | Transferring Files Using A Virtualized Application - Approaches for transferring a file using a virtualized application. A virtualized application executes within a virtual machine residing on a physical machine. When the virtualized application is instructed to download a file stored external to the physical machine, the virtualized application displays an interface which enables at least a portion of a file system, maintained by a host OS, to be browsed while preventing files stored within the virtual machine to be browsed. Upon the virtualized application receiving input identifying a target location within the file system, the virtualized application stores the file at the target location. The virtualized application may also upload a file stored on the physical machine using an interface which enables at least a portion of a file system of a host OS to be browsed while preventing files in the virtual machine to be browsed. | 12-25-2014 |