Patent application number | Description | Published |
20110289332 | METHOD AND APPARATUS FOR POWER MANAGEMENT IN A MULTI-PROCESSOR SYSTEM - Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt. | 11-24-2011 |
20110296412 | APPROACHES FOR SECURING AN INTERNET ENDPOINT USING FINE-GRAINED OPERATING SYSTEM VIRTUALIZATION - Approaches for executing untrusted software on a client without compromising the client using micro-virtualization to execute untrusted software in isolated contexts. A template for instantiating a virtual machine on a client is identified in response to receiving a request to execute an application. After the template is identified, without human intervention, a virtual machine is instantiated, using the template, in which the application is to be executed. The template may be selected from a plurality of templates based on the nature of the request, as each template describe characteristics of a virtual machine suitable for a different type of activity. Selected resources such as files are displayed to the virtual machines according to user and organization policies and controls. When the client determines that the application has ceased to execute, the client ceases execution of the virtual machine without human intervention. | 12-01-2011 |
20120144215 | MAXIMUM CURRENT LIMITING METHOD AND APPARATUS - The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current. | 06-07-2012 |
20120144221 | LOAD STEP MITIGATION METHOD AND APPARATUS - A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation. | 06-07-2012 |
20120159123 | CSTATE BOOST METHOD AND APPARATUS - A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State. | 06-21-2012 |
20120159198 | PROCESSOR POWER LIMIT MANAGEMENT - A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target. | 06-21-2012 |
20120159224 | HARDWARE ASSISTED PERFORMANCE STATE MANAGEMENT BASED ON PROCESSOR STATE CHANGES - A processor is configured to support a plurality of performance states and idle states. The processor includes a first programmable location associated with a first idle state and configured to store first entry performance state (P-State) information. The first entry P-State information identifies a first entry P-State. The processor is configured to receive a request to enter the first idle state, retrieve the first entry P-State information and enter the first entry P-State. The processor may include a second programmable location associated with the first idle state and configured to store first exit P-State information. The first exit P-State information identifies a first exit P-State. The processor may be configured to receive a request to exit the first idle state, retrieve the first exit P-State information and enter the first exit P-State. | 06-21-2012 |
20130024829 | METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT - Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state. | 01-24-2013 |
20130055256 | APPROACHES FOR AUTOMATED MANAGEMENT OF VIRTUAL MACHINES FOR RUNNING UNTRUSTED CODE SAFELY - Approaches for transferring data to a client by safely receiving the data in or more virtual machines. In response to the client determining that digital content, originating from an external source, is to be received or processed by the client, the client identifies, without human intervention, one or more virtual machines, executing or to be executed on the client, into which the digital content is to be stored. In doing so, the client may consult policy data to determine a placement policy, a containment policy, and a persistence policy for any virtual machine to receive the digital content. In this way, digital content, such as executable code or interpreted data, of unknown trustworthiness may be safely received by the client without the possibility of any malicious code therein from affecting any undesirable consequence upon the client. | 02-28-2013 |
20130132691 | APPROACHES FOR EFFICIENT PHYSICAL TO VIRTUAL DISK CONVERSION - Approaches for providing a guest operating system to a virtual machine. A read-only copy of one or more disk volumes, including a boot volume, is created. A copy of a master boot record (MBR) for the one or more disk volumes is also stored. The read-only copy may be, but need not be, made using a Volume Shadow Copy Service (VSS). A virtual disk, for use by the virtual machine, is created based on the read-only copy of the one or more disk volumes and the copy of the master boot record (MBR), wherein the virtual disk comprises the guest operating system used by the virtual machine. In this way, a single installed operating system may provide both the host operating system and the guest operating system. | 05-23-2013 |
20140380315 | Transferring Files Using A Virtualized Application - Approaches for transferring a file using a virtualized application. A virtualized application executes within a virtual machine residing on a physical machine. When the virtualized application is instructed to download a file stored external to the physical machine, the virtualized application displays an interface which enables at least a portion of a file system, maintained by a host OS, to be browsed while preventing files stored within the virtual machine to be browsed. Upon the virtualized application receiving input identifying a target location within the file system, the virtualized application stores the file at the target location. The virtualized application may also upload a file stored on the physical machine using an interface which enables at least a portion of a file system of a host OS to be browsed while preventing files in the virtual machine to be browsed. | 12-25-2014 |
Patent application number | Description | Published |
20090149253 | VIDEO SWITCHER AND TOUCH ROUTER METHOD FOR A GAMING MACHINE - A gaming method for presenting both gaming content based video signals and secondary video signals over a single display using a Display Manager is disclosed. The Display Manager is placed between the Master Gaming Controller and its Main Game Display and any Secondary Display and between the Player Tracking Unit connected to the casino system network (e.g., player tracking device) and its System display. The Display Manager receives one or more video signals from the Master Gaming Controller and one or more video signals from the system device and displays one or multiple video signals on one or more shared displays. One of video signals may be presented alone on one of the displays, with the other signal absent from that shared display, or multiple signals may be simultaneously displayed on one of the shared displays. The screen may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency by allowing the background signal to be partially or completely visible. Also, the overlaid signal may provide different levels of transparency in different areas of the display, effectively superimposing an image on top of the background signal. The Display Manager receives commands from a device, directing it how to split, overlay, superimpose, and otherwise share the display among the video input signals. | 06-11-2009 |
20090149254 | VIDEO SWITCHER AND TOUCH ROUTER SYSTEM FOR A GAMING MACHINE - A Display Manager is placed between the Master Gaming Controller and its Main Game Display and any Secondary Display and between the Player Tracking Unit connected to the casino system network (e.g., player tracking device) and its System display. The Display Manager receives one or more video signals from the Master Gaming Controller and one or more video signals from the system device and displays one or multiple video signals on one or more shared displays. One of the video signals may be presented alone on one of the displays, with the other signal absent from that shared display, or multiple signals may be simultaneously displayed on one of the shared displays. The screen may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency by allowing the background signal to be partially or completely visible. Also, the overlaid signal may provide different levels of transparency in different areas of the display, effectively superimposing an image on top of the background signal. The Display Manager receives commands from a device, directing it how to split, overlay, superimpose, and otherwise share the display among the video input signals. | 06-11-2009 |
20090258697 | GAMING MACHINE HAVING A CURVED DISPLAY WITH A VIDEO SWITCHER AND TOUCH ROUTER SYSTEM - Gaming machines projecting video images onto a curved display are disclosed herein. A Display Manager receives one or more video signals from a Master Gaming Controller and one or more video signals from the system device and displays one or multiple video signals on the curved display. The Display Manager sends the multiple video signals to a digital light emitting projector which projects the multiple video signals simultaneously on the curved display. The curved display may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency by allowing the background signal to be partially or completely visible. The Display Manager receives commands from a device, directing it how to split, overlay, superimpose, and otherwise share the display among the video input signals. | 10-15-2009 |
20120142409 | System and Method for Providing a System Generated In-Game Bonus in a Gaming Environment - A gaming system, terminal and method where a bonus is derived from multiple sources including system based and local sources and is delivered to a gaming machine by providing one or more additional game(s), altered games or altered features at the gaming machine instead of a direct award of the prize. The gaming system, terminal and method also provides for selection between various game features with different expected values for delivery of the bonus. | 06-07-2012 |
20120220360 | GAMING MACHINE HAVING A CURVED DISPLAY WITH A VIDEO SWITCHER AND TOUCH ROUTER SYSTEM - Gaming machines projecting video images onto a curved display are disclosed herein. A display manager receives one or more video signals from a controller and one or more video signals from the system device and displays one or multiple video signals on the curved display. The display manager sends the multiple video signals to a projector which projects the multiple video signals on the curved display. The curved display may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency by allowing the background signal to be partially or completely visible. The display manager the video signals regarding how to split, overlay, superimpose, and otherwise share the display among the video input signals. | 08-30-2012 |
20120258803 | VIDEO SWITCHER AND TOUCH ROUTER METHOD FOR A GAMING MACHINE - A gaming method for presenting both gaming content based video signals and secondary video signals over a single display using a Display Manager is disclosed. The Display Manager receives one or more video signals from a Gaming Controller and one or more video signals from a system device, and then displays one or multiple video signals on one or more shared displays. The screen may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency by allowing the background signal to be partially or completely visible. The Display Manager splits, overlays, superimposes, or otherwise shares the display among the video input signals. A touch router device interprets touches at a touch screen shared display to transform coordinates to enable interpretation of the player's touch inputs. | 10-11-2012 |
20130123010 | VIDEO SWITCHER AND TOUCH ROUTER METHOD FOR MULTI-LAYER DISPLAYS - A gaming method for presenting both gaming content based video signals and secondary video signals over a multi-layer touch screen display using a multiple Display Manager system is disclosed. First and second display managers are configured to receive game content video signals from a gaming controller and secondary video signals from a secondary video source. The first display manager is in communication with a front layer of the touch screen display and the second display manager is in communication with a back layer of the touch screen display. The screen may be split between multiple signals, or one or more signals may overlay one or more background signals. The overlaid signals may completely obscure the background signals, or they may provide a level of transparency. A touch router device interprets touches at a touch screen shared display to transform coordinates to enable interpretation of the player's touch inputs. | 05-16-2013 |
20130310179 | VIDEO SWITCHER AND TOUCH ROUTER SYSTEM FOR A GAMING MACHINE - A gaming system is disclosed for presenting both game content and secondary content on a single display. The gaming system includes: a touch screen game display configured to display content, a gaming controller configured to generate game content, and a secondary controller configured to generate secondary content. The display manager scales at least one of the game content and the secondary content to an altered size, enabling the game content from the gaming controller to be rendered with the secondary content from the secondary controller on the touch screen game display. The gaming system also includes a coordinate transformation calculation device that receives coordinates from an input on the touch screen game display and accommodates any scaling or shifting performed on at least one of the game content and the secondary content to determine transformed coordinates corresponding to the altered size of the rendered content. | 11-21-2013 |
20140080590 | System and Method for Providing Loyalty-Based Virtual Objects Across Various Media Including Gaming Devices - Gaming systems and methods are set forth designed to promote user loyalty with an enterprise. The user obtains a virtual object such as a virtual dog and earns the ability to acquire accessories or upgrades for their virtual dog through interaction with the enterprise. Certain accessories or upgrades may only be acquired or restored at a physical, brick and mortar venue for the enterprise to encourage the user to visit the venue. Acquisition of attributes such as accessories and upgrades may provide a basis for tournaments and prizes. The virtual object may be accessed and displayed at terminals at the venue or at remote devices. Acquisition of virtual objects may be used to qualify the user for a feature such as a progressive jackpot game. | 03-20-2014 |
20140155167 | VIDEO SWITCHER AND TOUICH ROUTER METHOD FOR A GAMING MACHINE - A method is described for presenting video signals from a first video source and one or more second video sources on a single touch screen display. The method includes: enabling display of primary content from a first video signal and secondary content from a second video signal on the touch screen display, using a display manager, in an adjacent or overlapping condition by scaling or shifting one of the first video signal(s) or the second video signal(s) to alter the size and to render the first video signal with the second video signal(s); and calculating a coordinate transformation, using a touch router device, on coordinates received from the touch screen display that correspond to the presentation at the touch screen display of the video signals and to accommodate any scaling or shifting performed on the first video signal(s) or the second video signal(s). | 06-05-2014 |
20150057081 | VIDEO SWITCHER AND TOUCH ROUTER SYSTEM FOR A GAMING MACHINE - A gaming system is disclosed for presenting both game content and secondary content on a single display. The gaming system includes: a touch screen game display configured to display content, a gaming controller configured to generate game content, and a secondary controller configured to generate secondary content. The display manager scales at least one of the game content and the secondary content to an altered size, enabling the game content to be rendered with the secondary content on the touch screen game display. The gaming system also includes a coordinate transformation calculation device that receives coordinates from an input on the touch screen game display and accommodates any scaling or shifting performed on at least one of the game content and the secondary content to determine transformed coordinates corresponding to the altered size of the rendered content prior to routing the transformed coordinates to the proper gaming or secondary controller. | 02-26-2015 |
Patent application number | Description | Published |
20080237680 | Enabling flash cell scaling by shaping of the floating gate using spacers - According to embodiments of the invention, an inverted “T” shaped gate can be formed for transistor flash memory cells to reduce feature sizes, to reduce pitch size, to increase gate coupling ratio and/or to reduce parasitic capacitive effects between adjacent flash cells or cell floating gates, such as with optimization of control gate distance between field gates. Such feature sizes include channel width; isolation region width; width of a portion of a gate electrode and/or half-pitch distance between adjacent cells or rows of transistors (e.g., cells). | 10-02-2008 |
20100155807 | Apparatus and methods for improved flash cell characteristics - Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed. | 06-24-2010 |
20120137048 | METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES - A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module. | 05-31-2012 |
20130268726 | Dual Mode Write Non-Volatile Memory System - Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments. | 10-10-2013 |
20130343129 | EXTENDED SELECT GATE LIFETIME - A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command. | 12-26-2013 |
20140006847 | Defect Management in Memory Systems | 01-02-2014 |
20140047302 | CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY - Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. | 02-13-2014 |
20140082460 | DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE - Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed. | 03-20-2014 |
20140089561 | Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory - Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed. | 03-27-2014 |
20140089762 | Techniques Associated with a Read and Write Window Budget for a Two Level Memory System - Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed. | 03-27-2014 |
20140122963 | IDENTIFICATION OF NON-VOLATILE MEMORY DIE FOR USE IN REMEDIAL ACTION - Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die. | 05-01-2014 |
20140149825 | SCALING FACTORS FOR HARD DECISION READS OF CODEWORDS DISTRIBUTED ACROSS DIE - Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword. | 05-29-2014 |
20140164863 | ADAPTIVE MOVING READ REFERENCES FOR MEMORY CELLS - Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed. | 06-12-2014 |
20140245096 | SINGLE-BIT ERROR CORRECTION - Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed. | 08-28-2014 |
20140258804 | REDUCED UNCORRECTABLE MEMORY ERRORS - Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively. | 09-11-2014 |
20140281203 | MANAGING DISTURBANCE INDUCED ERRORS - In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells. | 09-18-2014 |
20140297924 | NONVOLATILE MEMORY ERASURE TECHNIQUES - Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed. | 10-02-2014 |
20140307507 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 10-16-2014 |
20140370664 | WORD LINE AND BIT LINE PROCESSING FOR CROSS-POINT MEMORIES - Techniques for fabricating cross-point memory devices are disclosed in which word line (WL) and/or bit line (BL) processing is separate from cross-point memory memory-material processing, thereby providing an advantageous increase in thickness of the WL and/or BL metal that avoids an increase in the WL and BL resistances as feature sizes for cross-point memories scale smaller. | 12-18-2014 |
20140374686 | THERMAL-DISTURB MITIGATION IN DUAL-DECK CROSS-POINT MEMORIES - A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives. | 12-25-2014 |
20150019922 | Techniques for Adaptive Moving Read References for Memory Cell Read Error Recovery - Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples, priorities may be adaptively assigned to entries included in the MRR table. The entries may be ordered for use based on the assigned priorities. In other examples, the MRR table may be ordered for use such that entries with a single MRR value for each read reference value may be used first over entries having multiple MRR values for each read reference value. For these other examples, the MRR table may be adaptively reordered based on which entries were successful or unsuccessful in recovering from a read error but may still be arranged to have single MRR value entries used first for use to recover from another read error. | 01-15-2015 |
20150055407 | SET AND RESET OPERATION IN PHASE CHANGE MEMORY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed. | 02-26-2015 |
20150078075 | PROGRAMMING MEMORY CELLS USING A PROGRAM PULSE - Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse. | 03-19-2015 |
20150078088 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 03-19-2015 |
20150089120 | REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY - Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed. | 03-26-2015 |
20150089310 | USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY - Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed. | 03-26-2015 |
Patent application number | Description | Published |
20090217021 | SYSTEM AND METHOD FOR FAST RESTART OF A GUEST OPERATING SYSTEM IN A VIRTUAL MACHINE ENVIRONMENT - The present invention provides a system and method for fast restart of a guest operating system executing on a virtual machine operating system in a virtual machine environment. During initialization, the guest operating system saves a set of checkpoint information to persistent storage. Upon detection of an error condition during operation, the guest operating system begins a re-initialization procedure in accordance with an illustrative embodiment of the present invention. During the re-initialization procedure, the guest operating system retrieves the checkpoint information and configures itself using the retrieved information. By utilizing the retrieved information, the guest operating system avoids the need to perform lengthy configuration discovery routines, thereby shortening the re-initialization time substantially. | 08-27-2009 |
20090271402 | Deduplication of Data on Disk Devices Based on a Threshold Number of Sequential Blocks - Deduplication of data on disk devices based on a threshold number (THN) of sequential blocks is described herein, the threshold number being two or greater. Deduplication may be performed when a series of THN or more received blocks (THN series) match a sequence of THN or more stored blocks (THN sequence), whereby a sequence comprises blocks stored on the same track of a disk device. Deduplication may be performed using a block-comparison mechanism comprising metadata entries of stored blocks and a mapping mechanism containing mappings of deduplicated blocks to their matching blocks. The mapping mechanism may be used to perform later read requests received for the deduplicated blocks. The deduplication described herein may reduce the read latency as the number of seeks between tracks may be reduced. Also, when a seek to a different track is performed, the seek time cost is spread over THN or more blocks. | 10-29-2009 |
20090320042 | SYSTEM AND METHOD FOR ACHIEVING HIGH PERFORMANCE DATA FLOW AMONG USER SPACE PROCESSES IN STORAGE SYSTEM - Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate Input/Output requests without issuing system calls (and entering kernel mode). The multiple user spaces processes can initiate requests serviced by a user space device driver by sharing a read-only address space that maps the entire physical memory one-to-one. In addition, a user space process can initiate communication with another user space process by use of transmit and receive queues similar to transmit and receiver queues used by hardware devices. And, a mechanism of ensuring that virtual addresses that work in one address space reference the same physical page in another address space is used. | 12-24-2009 |
20110131390 | Deduplication of Data on Disk Devices Using Low-Latency Random Read Memory - Deduplication of data using a low-latency random read memory (LLRRM) is described herein. Upon receiving a block, if a matching block stored on a disk device is found, the received block is deduplicated by producing an index to the address location of the matching block. In some embodiments, a matching block having a predetermined threshold number of associated indexes that reference the matching block is transferred to LLRRM, the threshold number being one or greater. Associated indexes may be modified to reflect the new address location in LLRRM. Deduplication may be performed using a mapping mechanism containing mappings of deduplicated blocks to matching blocks, the mappings being used for performing read requests. Deduplication described herein may reduce read latency as LLRRM has relatively low latency in performing random read requests relative to disk devices. | 06-02-2011 |
20140109101 | EFFECTIVE SCHEDULING OF PRODUCER-CONSUMER PROCESSES IN A MULTI-PROCESSOR SYSTEM - A novel technique for improving throughput in a multi-core system in which data is processed according to a producer-consumer relationship by eliminating latencies caused by compulsory cache misses. The producer and consumer entities run as multiple slices of execution. Each such slice has an associated execution context that comprises of the code and data that particular slice would access. The execution contexts of the producer and consumer slices are small enough to fit in the processor caches simultaneously. When a producer entity scheduled on a first core completed production of data elements as constrained by the size of cache memories, a consumer entity is scheduled on that same core to consume the produced data elements. Meanwhile, a second slice of the producer entity is moved to another core and a second slice of a consumer entity is scheduled to consume elements produced by the second slice of the producer. | 04-17-2014 |
20140189434 | SYSTEM AND METHOD FOR ACHIEVING HIGH PERFORMANCE DATA FLOW AMONG USER SPACE PROCESSES IN STORAGE SYSTEMS - Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate Input/Output requests without issuing system calls (and entering kernel mode). The multiple user spaces processes can initiate requests serviced by a user space device driver by sharing a read-only address space that maps the entire physical memory one-to-one. In addition, a user space process can initiate communication with another user space process by use of transmit and receive queues similar to transmit and receiver queues used by hardware devices. And, a mechanism of ensuring that virtual addresses that work in one address space reference the same physical page in another address space is used. | 07-03-2014 |
Patent application number | Description | Published |
20100332910 | SYSTEM AND METHOD TO REDUCE TRACE FAULTS IN SOFTWARE MMU VIRTUALIZATION - A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed. | 12-30-2010 |
20120011504 | ONLINE CLASSIFICATION OF MEMORY PAGES BASED ON ACTIVITY LEVEL - Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold. | 01-12-2012 |
20120110236 | System and Method to Prioritize Large Memory Page Allocation in Virtualized Systems - The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization. | 05-03-2012 |
20130138864 | SYSTEM AND METHOD TO REDUCE TRACE FAULTS IN SOFTWARE MMU VIRTUALIZATION - A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed. | 05-30-2013 |
20130205062 | SYSTEM AND METHOD TO PRIORITIZE LARGE MEMORY PAGE ALLOCATION IN VIRTUALIZED SYSTEMS - The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization. | 08-08-2013 |
20140317375 | SYSTEM AND METHOD TO PRIORITIZE LARGE MEMORY PAGE ALLOCATION IN VIRTUALIZED SYSTEMS - The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization. | 10-23-2014 |
Patent application number | Description | Published |
20090160696 | CONFIGURABLE RADAR DETECTION AND AVOIDANCE SYSTEM FOR WIRELESS OFDM TRANCEIVERS - The present invention relates generally to wireless transceivers, and more particularly but not exclusively to radar detection and avoidance methodologies for wireless devices including transceivers. In one or more implementations, a method for detecting radar operating in the unlicensed 5.25-5.35 and 5.47-10.725 GHz radio bands, using wireless devices, such as WiFi AP, are provided. A WiFi AP is used to automatically detect the presence of radar on all channels in these bands, alert all of its clients, and move to another channel that is known to be devoid of radar using one or more implementations. | 06-25-2009 |
20100315952 | METHOD AND SYSTEM TO DETECT PACKETS OF DIFFERENT FORMATS IN A RECEIVER - A method and system of communicating packets and detecting packets are disclosed. In a first aspect, the method and system comprise enabling the detection of a very high throughput (VHT) signal field. The VHT signal field is distinguishable from other signal fields, wherein the VHT signal field allows for a backward compatibility with other devices. In a second aspect, the method and system comprise initializing the device to be in receive mode and receiving at least one signal field symbol and detecting the presence of additional signal field symbols. The method and system further include distinguishing a very high throughput (VHT) signal field from other signal field symbols and decoding the VHT signal field parameters uniquely describing the VHT packet format. | 12-16-2010 |
20100315953 | METHOD AND SYSTEM TO DETECT PACKETS OF DIFFERENT FORMATS IN A RECEIVER - A method and system of communicating packets and detecting packets are disclosed. In a first aspect, the method and system comprise enabling the detection of a very high throughput (VHT) signal field. The VHT signal field is distinguishable from other signal fields, wherein the VHT signal field allows for a backward compatibility with other devices. In a second aspect, the method and system comprise initializing the device to be in receive mode and receiving at least one signal field symbol and detecting the presence of additional signal field symbols. The method and system further include distinguishing a very high throughput (VHT) signal field from other signal field symbols and decoding the VHT signal field parameters uniquely describing the VHT packet format. | 12-16-2010 |
20100316169 | METHOD AND SYSTEM FOR OPERATING A MIMO DECODER - Varying embodiments of the present invention provide a MIMO apparatus, such as a transceiver and a method of operation thereof. In an embodiment, the transceiver employs a parallelized., two-stage pipeline architecture that reduces the overall latency of the system. This reduction in latency translates to cost savings and higher data rates for the same hardware clock speed. | 12-16-2010 |
20110182192 | METHOD AND APPARATUS FOR CALIBRATION OF AN IMPLICIT BEAMFORMING WIRELESS SYSTEM - A first embodiment is a method of calibrating an implicit beamforming wireless system wherein the implicit wireless system comprises a beamformer and a beamformee. The method comprises associating the beamformer with the beamformee, sending a sounding packet from the beamformer to the beamformee, receiving a sounding response at the beamformer wherein the sounding response contains explicit channel state information as estimated by beamformee, computing implicit channel state information at the beamformer based on transmissions from the beamformee, passing explicit and implicit channel state information into the beamformer, computing a set of compensation parameters and loading the set of compensation parameters into the beamformer thereby enabling the beamformer to implicitly beamform to a device that does not support explicit beamforming. | 07-28-2011 |
20110274002 | METHOD AND SYSTEM OF OPERATING A MULTI-USER SYSTEM - A method and system is disclosed for grouping the multiple stations connected to an access point (AP). The system and method comprise sending a sounding packet to a plurality of stations, wherein the stations may be all or part of the stations that are located within the range of the AP. The stations that receive the sounding packets respond to the AP, and the AP determines the channel state information (CSI) from the responses. According to the CSI, the AP divides the multiple stations into several groups. According to an embodiment of the present invention, a confirmation step is performed to each group of stations, respectively. The AP sends a second sounding packet to each group of stations, and verifies the CSI between each station group by group. Therefore, the method and system provides for monitoring the validation of each group by periodically sending sounding packets to each group. | 11-10-2011 |
20110274003 | METHOD AND SYSTEM OF OPERATING A MULTI-USER SYSTEM - A method and system is disclosed for grouping the multiple stations connected to an access point (AP). The system and method comprise sending a sounding packet to a plurality of stations, wherein the stations may be all or part of the stations that are located within the range of the AP. The stations that receive the sounding packets respond to the AP, and the AP determines the channel state information (CSI) from the responses. According to the CSI, the AP divides the multiple stations into several groups. According to an embodiment of the present invention, a confirmation step is performed to each group of stations, respectively. The AP sends a second sounding packet to each group of stations, and verifies the CSI between each station group by group. Therefore, the method and system provides for monitoring the validation of each group by periodically sending sounding packets to each group. | 11-10-2011 |
20120002622 | METHOD FOR SIGNAL SPACE PARTITION AND ASSIGNMENT AND APPARATUS USING THE SAME - A method and system utilized in a wireless communication system is disclosed. The communication system includes a transmitter and one or more of stations in communication therewith. The method and system comprise encoding a data assignment of each of the data streams associated with a packet into a plurality of bits, wherein the plurality of bits are within a header of the packet within the transmitter. The method and system also includes decoding the plurality of bits by the one or more stations to allow the one or more stations to obtain the appropriate data stream. | 01-05-2012 |
20120002652 | METHOD AND SYSTEM FOR IMPROVING THE EFFICIENCY OF PACKET TRANSMISSION IN A MULTI-USER WIRELESS COMMUNICATION SYSTEM - A method and system utilized in a wireless communication system transmitting and receiving a multi-user packet is disclosed. The communication system includes a transmitter and a plurality of users in communication therewith. The method and system comprise determining a lowest coding scheme for transmitting the packet; and deriving a coding rate for the efficient transmission of the packet from a standard coding rate by de-puncturing bits in the packet. A system and method in accordance with the present invention provides for an efficient utilization of packet length, and improves the reliability by improving SNR, by lowering the MCS, un-puncturing, and/or repetition. More efficient packed data rates are also provided and both Tx and Rx compute parameters independently. | 01-05-2012 |
20120009961 | METHOD AND APPARATUS FOR BEAMFORMING IN A WIRELESS COMMUNICATION SYSTEM - Varying embodiments of the present invention describes a method and apparatus for beamforming in a wireless communication system. A first embodiment is a method for beamforming in a wireless communication system, the system comprising a transmitter and a receiver. The method comprises initiating beamforming on a communication channel between the transmitter and the receiver wherein the communication channel comprises at least two transmit chains, controlling the beamforming by mapping the data stream(s) to the at least two transmit chains and controlling the scaling of the at least two transmit chains within a transmit power constraint. | 01-12-2012 |
20120039315 | METHOD AND SYSTEM TO DETECT PACKETS OF DIFFERENT FORMATS - A method and system in accordance with the present invention presents a new packet structure and an improved method for detecting the packet. The method and system comprise adding an additional field to the packet structure to allow for a sufficient time to process a very high throughput (VHT) signal field; and enabling the detection of the VHT signal field of the packet structure. The VHT signal field is distinguishable from other signal fields and the VHT signal field allows for a backward compatibility with other devices. | 02-16-2012 |
20120093025 | METHOD AND SYSTEM FOR DETECTING PACKET TYPE - It is therefore an object of the present invention to provide a method for detecting different packet type. The method comprises, determining whether the rate of a received packet corresponds to a predetermined rate, derotating the bits of a symbol in the received packet, obtaining an energy different of the symbol at different axes, and determining the type of the received packet according to the energy difference. | 04-19-2012 |
20120314594 | MEASURING AND IMPROVING MULTIUSER DOWNLINK RECEPTION QUALITY IN WIRELESS LOCAL AREA NETWORKS - Embodiments for improving multi-user downlink reception quality in WLANS are disclosed. In one embodiment, a method includes receiving, at a station, at least one multi-user sounding packet from an access point. The method also includes determining a sum of desired signal strengths from the at least one received sounding packet. The method also includes determining a sum of interference signal strengths from the at least one received sounding packet. The method also includes generating link quality metrics based on a ratio of the sum of desired signal strengths to the sum of interference signal strengths. | 12-13-2012 |
20130243064 | EXPERT ANTENNA CONTROL SYSTEM - A method and system for actively selecting antenna sets for a client are disclosed. In a first aspect, the method comprises sending a first channel packet from a transmitter to a receiver and sending a second channel packet corresponding to the received first channel packet from the receiver to the transmitter. The method includes collecting statistics of an antenna set related to the sending of the first and the second channel packets. The method includes comparing the collected statistics to previously collected statistics of another antenna set to select one of the antenna set and the another antenna set. In a second aspect, the system comprises a processor and a memory device coupled to the processor, wherein the memory device stores an application which, when executed by the processor, causes the processor to carry out the steps of the method. | 09-19-2013 |
20130251074 | DEMODULATING DATA STREAMS - Embodiments for demodulating data streams are disclosed. In one embodiment, a method includes receiving, at a multiple-input device, a plurality of data streams. The method also includes determining a degree of correlation among the plurality of data streams. The method also includes selecting a demodulator based on the degree of correlation. | 09-26-2013 |
20140064390 | FREQUENCY DOMAIN EQUALIZER FOR A BEAMFORMED SYSTEM - A method, system, and computer program product for beamforming in a wireless communication system is disclosed. The method, system, and computer program product comprise a plurality of transmit antennas for a transmitter and at least one receive antenna for a receiver. The method, system, and computer program product comprise: initiating beamforming on a communication channel between the plurality of transmit antennas and the at least one receive antenna. The communication channel includes two data streams. A received signal to noise ratio (SNR) on one of the two data streams is weaker than a received SNR of the other data stream. The method, system, and computer program product include reallocating the transmit power between the stronger stream and the weaker stream to provide improved channel performance. | 03-06-2014 |
20140348082 | METHOD AND SYSTEM OF OPERATING A MULTI-USER SYSTEM - A method and system is disclosed for grouping the multiple stations connected to an access point (AP). The system and method comprise sending a sounding packet to a plurality of stations, wherein the stations may be all or part of the stations that are located within the range of the AP. The stations that receive the sounding packets respond to the AP, and the AP determines the channel state information (CSI) from the responses. According to the CSI, the AP divides the multiple stations into several groups. According to an embodiment of the present invention, a confirmation step is performed to each group of stations, respectively. The AP sends a second sounding packet to each group of stations, and verifies the CSI between each station group by group. Therefore, the method and system provides for monitoring the validation of each group by periodically sending sounding packets to each group. | 11-27-2014 |
20150071168 | METHOD AND SYSTEM FOR IMPROVING THE EFFICIENCY OF PACKET TRANSMISSION IN A MULTI-USER WIRELESS COMMUNICATION SYSTEM - A method and system utilized in a wireless communication system transmitting and receiving a multi-user packet is disclosed. The communication system includes a transmitter and a plurality of users in communication therewith. The method and system comprise determining a lowest coding scheme for transmitting the packet; and deriving a coding rate for the efficient transmission of the packet from a standard coding rate by de-puncturing bits in the packet. A system and method in accordance with the present invention provides for an efficient utilization of packet length, and improves the reliability by improving SNR, by lowering the MCS, un-puncturing, and/or repetition. More efficient packed data rates are also provided and both Tx and Rx compute parameters independently. | 03-12-2015 |