Patent application number | Description | Published |
20090261907 | INTEGRATED CIRCUIT HAVING ON DIE STRUCTURE PROVIDING CAPACITANCE IN AMPLIFIER FEEDBACK PATH - An amplifier structure includes shield conductors that are provided spatially adjacent to elongated feedback signal lines that couple a feedback circuit to an amplifier input. The shield conductors are provided between the feedback signal lines and a ground plane, which interrupts a parasitic capacitance that otherwise would be established between the feedback signal line and ground. The shield conductors are electrically coupled to the amplifier's outputs which create a capacitance between the output terminal and the feedback signal line. In some embodiments, the capacitance generated between the output terminal and the feedback signal line can suffice as a capacitor in a feedback path of the amplifier and be contained in an integrated circuit die on which the amplifier is manufactured. Optionally, a structure may be provided that eliminates common mode signals on the feedback lines while simultaneously preserving the common mode signals on the amplifier output terminals. In this option, a second amplifier is provided that, in response to common mode variations at the output terminal, generates counterbalancing voltage variations on a second circuit that is coupled to the feedback lines at their source. The two variations cancel each other out at nodes from which the feedback lines originate, which substantially reduces feedback common mode variation even when there is common mode variation at the output terminals. | 10-22-2009 |
20120268204 | APPARATUS AND METHOD FOR EQUALIZATION - Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor. | 10-25-2012 |
20130033326 | APPARATUS AND METHOD FOR DIGITALLY-CONTROLLED AUTOMATIC GAIN AMPLIFICATION - Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node. | 02-07-2013 |
20130034143 | APPARATUS AND METHOD FOR DIGITALLY-CONTROLLED ADAPTIVE EQUALIZER - Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer includes a first node configured to receive the input signal; a second node; and a programmable gain amplifier (PGA) having an adjustable gain. The PGA has an input electrically coupled to the first node, and an output electrically coupled to a third node. The equalizer also includes a high pass filter (HPF) having an input electrically coupled to the third node, and an output electrically coupled to the second node; and a control block configured to adjust one or more of the PGA or the HPF at least partly in response to a PGA output signal from the PGA or an HPF output signal from the HPF. | 02-07-2013 |
20130043937 | APPARATUS AND METHOD FOR ELECTRICAL BIASING - As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point. | 02-21-2013 |
20130271219 | APPARATUS AND METHODS FOR FREQUENCY COMPENSATION OF AN AMPLIFIER - Apparatus and methods for frequency compensation of an amplifier are provided. In one embodiment, an integrated circuit (IC) includes an amplifier configured to amplify an input signal to generate an output signal. The IC further includes an output pad configured to receive an output signal from the amplifier and a control pad for controlling the closed-loop bandwidth of the amplifier. A compensation capacitor is electrically connected between an input of the inverting amplification block and an output of the inverting amplification block, and a switchable capacitor is electrically connected between the input of the inverting amplification block and the control pad. The control pad can be electrically connected to a DC voltage source or to the output pad to control the amplifier's closed-loop bandwidth. | 10-17-2013 |
20130287084 | WIDE COMMON-MODE RANGE RECEIVER - A wide common-mode range receiver includes an input module, voltage level shift module, voltage level shift control module, and output module. The receiver can also include an equalizer. The receiver translates data originating from a circuit powered from an external voltage supply to a circuit powered by an internal voltage supply. The voltage level shift may be scaled based on differences between the voltage supplies or by determining the difference between an input common-mode voltage and a reference voltage, and driving a servo based on the difference. | 10-31-2013 |
20140037031 | METHODS FOR DIGITALLY-CONTROLLED AUTOMATIC GAIN AMPLIFICATION - Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node. | 02-06-2014 |