Kim, Ichon-Shi
Buem-Suck Kim, Ichon-Shi KR
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20110147886 | SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask. | 06-23-2011 |
Cheul-Hong Kim, Ichon-Shi KR
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20100075715 | APPARATUS AND METHOD FOR AUTOMATICALLY DETECTING PRESENCE OF EXTERNAL DEVICE IN MOBILE TERMINAL - In an apparatus and method for automatically detecting the presence of an external device in a port of a mobile terminal, the external device is automatically enabled without the additional operation of the mobile terminal when plugged into a jack. The mobile terminal may be safeguarded against severe damage being done thereto by mistakenly choosing options to enable an external device while an earphone/microphone set is plugged in the jack of a mobile terminal. | 03-25-2010 |
Chul Kim, Ichon-Shi KR
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20110128039 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal. | 06-02-2011 |
20110241653 | IMPEDANCE CALIBRATION APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT - An impedance calibration apparatus of a semiconductor integrated circuit includes: a D/A conversion unit configured to receive a code and generate an analog voltage depending on the code; a virtual code voltage generation unit configured to detect a level of the analog voltage and generate a plurality of virtual code voltages based on the level of the analog voltage; a comparison unit configured to receive the plurality of virtual code voltages and a reference voltage as inputs, and compare the plurality of virtual code voltages with the reference voltage to generate a plurality of comparison signals; and a code generation unit configured to receive the plurality of comparison signals and generate the code using the plurality of comparison signals. | 10-06-2011 |
20110292707 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines. | 12-01-2011 |
Dae Suk Kim, Ichon-Shi KR
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20120154008 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a master chip, first to n | 06-21-2012 |
Gyu-Hyun Kim, Ichon-Shi KR
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20100117235 | METAL LINE IN SEMICONDUCTOR DEVICE - A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer. | 05-13-2010 |
Hong Gyeom Kim, Ichon-Shi KR
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20110164451 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE FUSE - A semiconductor integrated circuit comprises a plurality of fuses arranged to be spaced apart from one another by predetermined intervals, and a page buffer electrically connected to the plurality of fuses and configured to determine whether to disconnect the fuses. The fuses comprise a NAND flash string. The NAND flash string comprises a drain select transistor connected to a bit line, a flash memory cell electrically connected to the drain select transistor, and a source select transistor connected between the flash memory cell and a ground terminal. | 07-07-2011 |
20110291744 | FUSE CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal. | 12-01-2011 |
Ho-Ung Kim, Ichon-Shi KR
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20090090985 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region contacting a portion of the isolation region under the gate pattern. | 04-09-2009 |
20120235248 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region contacting a portion of the isolation region under the gate pattern. | 09-20-2012 |
Hyung Soo Kim, Ichon-Shi KR
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20100090736 | DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled. | 04-15-2010 |
Hyun Seok Kim, Ichon-Shi KR
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20110235385 | SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE - A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines. | 09-29-2011 |
20110242869 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF - A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a vertical direction, among a plurality of memory banks included in the plurality of chips. | 10-06-2011 |
Jae-Hong Kim, Ichon-Shi KR
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20080277714 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a control gate formed along a first direction over a substrate, an active region formed over the substrate, the active region being defined along a second direction crossing the control gate and including a fin type protruding portion having rounded top corners at a region where the control gate and the active region overlap, a floating gate formed over a surface of the protruding portion of the active region below the control gate and formed to a substantially uniform thickness along the surface profile of the protruding portion of the active region, a tunneling insulation layer formed between the floating gate and the active region, and a dielectric layer formed between the floating gate and the control gate. | 11-13-2008 |
Jeong-Soo Kim, Ichon-Shi KR
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20090014875 | BONDING PAD FOR PREVENTING PAD PEELING AND METHOD FOR FABRICATING THE SAME - A bonding pad includes multiple metal layers, insulation layers filled between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer, where a bonding is performed, and the underlying metal layers. Peeling of the bonding pad can be prevented during the ball bonding by forming the fixing pin coupled to the edges of the bonding pad. The upper portion of the fixing pin is formed in a disk shape and a ball portion of the fixing pin is fixed by slits such that the peeling of the bonding pad can be further prevented. | 01-15-2009 |
20110018131 | BONDING PAD FOR PREVENTING PAD PEELING - A bonding pad includes multiple metal layers, insulation layers disposed between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer and an underlying metal layer of the multiple metal layers, where a bonding is performed on the uppermost metal layers. | 01-27-2011 |
Je Yoon Kim, Ichon-Shi KR
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20110267908 | REPAIR CIRCUIT AND REPAIR METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding to the memory block determined to have failed as a repair address, and an anti-fuse circuit that receives the repair address from the repair address detection circuit and electrically programs the repair address to store a programmed address. | 11-03-2011 |
Jong-Kuk Kim, Ichon-Shi KR
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20080242042 | METHOD FOR FABRICATING A CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer and a support layer on a substrate. A plurality of openings are formed by etching the support layer and the sacrificial layer. An electrode is formed in inner walls of the openings including sidewalls of the support layer patterned through etching. A portion of the patterned support layer is removed, and the sacrificial layer is also removed. | 10-02-2008 |
Jun-Ki Kim, Ichon-Shi KR
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20090121235 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases. | 05-14-2009 |
Ju Young Kim, Ichon-Shi KR
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20120133423 | SEMICONDUCTOR APPARATUS, SEMICONDUCTOR SYSTEM, AND METHOD FOR OUTPUTTING INTERNAL INFORMATION THEREOF - A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals. | 05-31-2012 |
Ki Han Kim, Ichon-Shi KR
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20110234279 | VARIABLE UNIT DELAY CIRCUIT AND CLOCK GENERATION CIRCUIT FOR SEMICONDUCTOR APPARATUS USING THE SAME - A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal. | 09-29-2011 |
Ki Up Kim, Ichon-Shi KR
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20110158013 | FUSE SET OF SEMICONDUCTOR MEMORY AND REPAIR DETERMINATION CIRCUIT USING THE SAME - A fuse set of a semiconductor memory includes a first fuse array and a second fuse array each configured to designate a column redundancy address; and a unit fuse circuit configured to select one of the first fuse array and the second fuse array based on a row address. | 06-30-2011 |
20110187411 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR CONTROLLING OUTPUT DRIVING FORCE - A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an output terminal; a terminal connecting unit configured to receive a determination signal and connect to or disconnect from the output terminal in response to the determination signal; a terminal sensing unit configured to sense the output terminal and output a terminal state signal; and a driving force determining unit configured to receive a reset signal and the terminal state signal and output the driving force control signal. | 08-04-2011 |
20120136611 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF - A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode. | 05-31-2012 |
Kwang Hyun Kim, Ichon-Shi KR
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20120106263 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 05-03-2012 |
Min Su Kim, Ichon-Shi KR
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20120275222 | NONVOLATILE MEMORY APPARATUS AND VERIFICATION METHOD THEREOF - A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit. | 11-01-2012 |
Ryeun Kwan Kim, Ichon-Shi KR
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20090087585 | DEPOSITION PROCESSES FOR TITANIUM NITRIDE BARRIER AND ALUMINUM - Embodiments described herein provide a method for forming two titanium nitride materials by different PVD processes, such that a metallic titanium nitride layer is initially formed by a PVD process in a metallic mode and a titanium nitride retarding layer is formed over a portion of the metallic titanium nitride layer by a PVD process in a poison mode. Subsequently, a first aluminum layer, such as an aluminum seed layer, may be selectively deposited on exposed portions of the metallic titanium nitride layer by a CVD process. Thereafter, a second aluminum layer, such as an aluminum bulk layer, may be deposited on exposed portions of the first aluminum layer and the titanium nitride retarding layer during an aluminum PVD process. | 04-02-2009 |
Se-Jun Kim, Ichon-Shi KR
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20110085405 | SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK - A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal. | 04-14-2011 |
20110286287 | SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION - Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage. | 11-24-2011 |
Seong-Yeon Kim, Ichon-Shi KR
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20080203432 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A transistor including a gate insulation layer, a gate, and source/drain regions, the transistor comprising a semiconductor layer formed under the gate insulation layer for use as a channel region in a substrate, wherein the semiconductor layer is formed of a material having a lower bandgap than silicon. | 08-28-2008 |
Sook-Joo Kim, Ichon-Shi KR
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20090218616 | TRANSISTOR HAVING VERTICAL CHANNEL AND METHOD FOR FABRICATING THE SAME - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 09-03-2009 |
20100308403 | TRANSISTOR HAVING VERTICAL CHANNEL - A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar. | 12-09-2010 |
Suk-Ki Kim, Ichon-Shi KR
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20100062598 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH METAL LINE - A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines. | 03-11-2010 |
Tae-Kyung Kim, Ichon-Shi KR
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20110186920 | SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE - A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer. | 08-04-2011 |
20130241011 | SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE - A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer. | 09-19-2013 |
Tae-Yun Kim, Ichon-Shi KR
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20080211553 | Delay locked loop in semiconductor memory device and method for generating divided clock therein - Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock. | 09-04-2008 |
Won Kim, Ichon-Shi KR
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20090111256 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled. | 04-30-2009 |
Yang Hee Kim, Ichon-Shi KR
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20110235385 | SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE - A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines. | 09-29-2011 |
Yil-Wook Kim, Ichon-Shi KR
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20110198701 | Transistor of Volatile Memory Device with Gate Dielectric Structure Capable of Trapping Charges and Method for Fabricating the Same - The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate. | 08-18-2011 |
Yong Ju Kim, Ichon-Shi KR
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20100090736 | DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled. | 04-15-2010 |
Yong Wook Kim, Ichon-Shi KR
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20090026528 | Flash Memory Cell and Method of Manufacturing the Same and Programming/Erasing Reading Method of Flash Memory Cell - Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time. | 01-29-2009 |
Yool-Guk Kim, Ichon-Shi KR
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20090040805 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation. | 02-12-2009 |
Youn-Cheul Kim, Ichon-Shi KR
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20110310682 | DELAY-LOCKED LOOP HAVING LOOP BANDWIDTH DEPENDENCY ON OPERATING FREQUENCY - Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its operating frequency. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its operating frequency. In this specific example, operating frequency is determined. This determination may be made directly, either by measuring operating frequency, or indirectly, by taking a measurement or reading, such as by reading a value for column address select latency. Once the operating frequency is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth of the delay-locked loop's loop filter. | 12-22-2011 |
Young Park Kim, Ichon-Shi KR
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20110271133 | ADDRESS OUTPUT TIMING CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal. | 11-03-2011 |
Young Won Kim, Ichon-Shi KR
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20110235385 | SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE - A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines. | 09-29-2011 |
You Sung Kim, Ichon-Shi KR
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20120275222 | NONVOLATILE MEMORY APPARATUS AND VERIFICATION METHOD THEREOF - A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a first current control signal, and a second current control signal, which correspond to the number of fail bits to be sensed and a deviation in cell current amounts flowing through the unit memory cells during a read operation, in response to a verification command; and a fail bit sensing unit configured to receive the reference current generation signal, the first current control signal, and the second current control signal from the controller in response to the verification command, and control at least one of a reference current amount and a data read current amount of the page buffer unit. | 11-01-2012 |