Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Kim, Icheon-Si
Beom Sik Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120221825 | NONVOLATILE MEMORY SYSTEM AND FEATURE INFORMATION SETTING METHOD - A nonvolatile memory system includes a controller and a nonvolatile memory apparatus, where the controller provides the nonvolatile memory apparatus with a first feature setting command or a second feature setting command according to device information of the nonvolatile memory apparatus in a mode change of the nonvolatile memory apparatus. | 08-30-2012 |
Chang Shuk Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100103720 | BIOSENSOR AND SENSING CELL ARRAY USING THE SAME - A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline). Ingredients of adjacent materials are separated based on electrical characteristics of ingredients by sensing magnetic susceptibility and dielectric constant depending on the sizes of the ingredients. | 04-29-2010 |
Cheol Kyun Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090235224 | Method for Processing Optical Proximity Correction - A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data. | 09-17-2009 |
| 20100017779 | Method for Decomposing Designed Pattern Layout and Method for Fabricating Exposure Mask Using the Same - A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time. | 01-21-2010 |
| 20100162195 | METHOD FOR DETECTING A WEAK POINT - A weak point detecting method of the present invention designs a target layout, and compensates an optical proximity effect for the target layout, thereafter, verifies the target layout in which the optical proximity effect is compensated by using an NILS of the target layout, thereby, enabling to reduce the time and cost in detecting a weak point for a full chip regardless of the size and form of a pattern. | 06-24-2010 |
| 20120167018 | Method for Decomposing a Designed Pattern Layout - A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time. | 06-28-2012 |
Choi Dong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080280216 | METHOD OF FORMING A HARD MASK PATTERN IN A SEMICONDUCTOR DEVICE - In a method of forming hard mask patterns in a semiconductor device, an etch mask has a pitch less than a resolution limitation of exposure equipment. The method includes forming first hard mask patterns through an exposure process utilizing photoresist patterns, forming a separation layer on a resulting structure including the first hard mask patterns, forming a second hard mask pattern in a space between the first hard mask patterns, and removing the exposed separation layer. | 11-13-2008 |
Dae-Seong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100135868 | SOFT X-RAY PHOTOIONIZATION CHARGER - A soft X-ray photoionization charger includes a housing having a chamber and an aperture formed on one side surface of the housing and joined to the chamber. The chamber forms a flow path of an aerosol containing particles. A photoionizer is fixed to the aperture of the housing. The photoionizer includes a head for irradiating soft X-rays into the chamber to neutralize the particles. A transparent window is mounted between the chamber and the head. The transparent window is made of a material permitting passage of the soft X-rays. The photoionization charger further includes a soft support ring arranged around the transparent window and tightly fitted to the aperture. | 06-03-2010 |
Dae Young Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090160000 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - An image sensor and a method for manufacturing the sensor are provided for reducing loss of light reflected from photodiodes, and thus, improving light efficiency. The method of manufacturing an image sensor can include providing a semiconductor substrate having a photodiode; and then forming a reflective film frame on the photodiode, the reflective film frame having sidewalls that are inclined with respect to the uppermost surface of the photodiode; and then forming an opening over the surface of the reflective film frame and corresponding to the photodiode by forming a reflective film on the sidewalls of the reflective film frame. | 06-25-2009 |
| 20110014553 | SEMICONDUCTOR DEVICE WITH A BULB-TYPE RECESS GATE - An exposure mask includes a plurality of active region patterns, and a plurality of recess patterns with a first line width, passing across the active region patterns, wherein the line width of at least one of the plurality of recess patterns neighboring one of the plurality of active region patterns is narrowed down into a second line width. | 01-20-2011 |
Dong Keun Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110205789 | Semiconductor memory apparatus - A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among the plurality of word lines in response to a row address which designates one word line; a global column switch block configured to select two different global bit lines among the plurality of global bit lines in response to column control signals; and a column decoder configured to generate the column control signals in response to a column address. | 08-25-2011 |
| 20120081955 | PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - A phase change random access memory device includes: a sense amplifier driving unit configured to compare an input voltage applied through an input signal line with a reference voltage and amplify an output signal in response to the comparison result; an input unit configured to receive an input signal from the input signal line and transmit the received signal to the sense amplifier driving unit; and a coupling prevention unit including a plurality of MOS transistors sharing a bulk bias, coupled between the sense amplifier driving unit and the input unit, and configured to control a sensing margin in response to a level of the input signal. | 04-05-2012 |
| 20120195113 | PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS - A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal. | 08-02-2012 |
Eun Jun Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120120290 | IMAGE SENSING DEVICE AND METHOD FOR OPERATING THE SAME - An image sensing device includes, inter alia, a ramp signal generation unit generating a ramp signal that decreases during first and second periods for finding data values corresponding to a pixel signal and an offset value, respectively. The image sensing device also includes a comparison unit compares the pixel signal with the ramp signal during the first period, and compares the ramp signal with an internally generated offset value during the second period. A first counting unit is configured to perform a counting operation during the first period, and a second counting unit configured to latch a count value of the first counting unit as a data value in response to the result of the first comparison operation during the first period, perform a down-count operation from the latched data value in response to the result of the second comparison operation during the second period, and latch a counting result. | 05-17-2012 |
Eun-Mi Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090087960 | METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE - A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer. | 04-02-2009 |
| 20100025806 | Semiconductor device and method of fabricating the same - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 02-04-2010 |
| 20110266634 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 11-03-2011 |
| 20110266648 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 11-03-2011 |
Gyung Tae Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120080750 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias. | 04-05-2012 |
Hak Joon Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090004610 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method and apparatus for manufacturing a semiconductor device is disclosed. In particular, the application discloses a method that performs a lithography process using a material capable of increasing a depth of focus so as to prevent efficiency of the lithography process from being degraded due to high integration of a semiconductor device, and a pressure-type bake oven as an apparatus for forming a high refractive material on a semiconductor substrate, having advantages of reducing manufacturing costs of a semiconductor manufacturing process and increasing efficiency of the lithography process. | 01-01-2009 |
| 20110151382 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method and apparatus for manufacturing a semiconductor device is disclosed. In particular, the application discloses a method that performs a lithography process using a material capable of increasing a depth of focus so as to prevent efficiency of the lithography process from being degraded due to high integration of a semiconductor device, and a pressure-type bake oven as an apparatus for forming a high refractive material on a semiconductor substrate, having advantages of reducing manufacturing costs of a semiconductor manufacturing process and increasing efficiency of the lithography process. | 06-23-2011 |
Ho Jin Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090249863 | VAPOR PHASE DECOMPOSITION DEVICE FOR SEMICONDUCTOR WAFER POLLUTANT MEASUREMENT APPARATUS AND DOOR OPENING AND CLOSING DEVICE - Provided is a vapor phase decomposition (VPD) device for a semiconductor wafer pollutant measurement apparatus and a door opening and closing device thereof. The VPD device includes: a rectangular vessel-shaped main body of the VPD device and a door which covers in a sealed form or opens the wafer inlet of the VPD device. Here, a predetermined space is formed in the inner portion of the rectangular vessel-shaped main body, support plates are formed on the bottom of the rectangular vessel-shaped main body and gas discharge and suction nozzles are located therein. In addition, a transparent see-through window is formed on the upper surface of the rectangular vessel-shaped main body, a detection electrode for controlling an inner atmosphere is formed at the center of the transparent see-through window, and one side surface of the rectangular vessel-shaped main body is opened to thus form a wafer inlet for introducing a wafer. The door opening and closing device includes: a forward and backward movement unit having cylinder loads, air cylinders, and plates, to make the door move forward and backward in order to open and close the wafer inlet of the main body of the VPD device; and an ascent and descent movement unit having a fixed plate, guide bars, a slide block, and a cylinder. | 10-08-2009 |
| 20090249896 | SCANNING ARM FOR SEMICONDUCTOR WAFER POLLUTANT MEASUREMENT APPARATUS AND SCANNING DEVICE USING THE SAME - Provided is a scanning arm which moves to collect pollutants on the surface of a semiconductor wafer, for use in a semiconductor wafer pollutant measurement apparatus, and a scanning device using the same the scanning arm includes: an X-axis portion; a Z-axis portion which is perpendicularly installed with the X-axis portion so as to move forward and backward along the X-axis portion; and a Y-axis portion which is perpendicularly installed with the Z-axis portion so as to move up and down with respect to the Z-axis portion. The scanning device includes: the scanning arm; and a scanning nozzle which is installed at the Y-axis portion, and inhales a scan solution from a reagent solution bottle to then discharge a reagent scan solution on the surface of a wafer which is located on a scan stage and simultaneously keep an inhalation condition and move along the surface of the wafer, to then inhale and keep the scan solution including pollutants sticked on the wafer surface. The X-axis portion, the Y-axis portion and the Z-axis portion includes a linear motion (LM) guide and a screw bar in an external casing, respectively, in which a slider is combined with the screw bar by a ball bushing combination so that the slider moves according to rotation of the screw bar. The scanning nozzle includes: a pumping portion; a support which supports the pumping portion; and a nozzle main body which is connected below the pumping portion. The scanning device for the semiconductor wafer pollutant measurement apparatus has a feature that collection and drying are simultaneously achieved by the scanning arm having a three-axis operational trace and a drier. | 10-08-2009 |
| 20090250569 | SCAN STAGE FOR SEMICONDUCTOR WAFER POLLUTANT MEASUREMENT APPARATUS - Provided is a scan stage for a semiconductor wafer pollutant measurement apparatus, which includes: a stage main body which comprises: a circular fixed housing; an adsorption plate which is rotatably installed in the inside of the fixed housing, at the center of which an adsorption path is formed, at the bottom of which a vacuum port is connected, and which is rotated by an external rotating force; and a step motor which is placed at the bottom of the fixed housing and connected with the adsorption plate; a base plate that is supported by pillars to form a lower space between the fixed housing of the stage main body and the base plate; a cylinder at the bottom of which a cylinder load is connected so that the base plate moves up and down; and support jigs that hold up a wafer in the outer side of the stage main body, in which three support jigs are disposed in proximity with the outer circumference of the stage main body. | 10-08-2009 |
Hong Lae Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090008731 | Image Sensor and Method for Manufacturing the Same - An image sensor and method of manufacturing the same are provided. The image sensor can include a photodiode on a substrate, an interlayer insulation layer on the photodiode, and a color filter layer on the interlayer insulation layer. The color filter layer can include a nonsensitive color resin. | 01-08-2009 |
Hyang Yul Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110244751 | FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - Provided is a fringe field switching mode liquid crystal display. The fringe field switching mode liquid crystal display includes a transparent common electrode having a predetermined shape and formed within the pixel area to adjust light transmittance by applying a voltage to the liquid crystal layer, and a transparent pixel electrode having a plurality of slits and formed above the transparent common electrode with an insulating layer interposed between the transparent common electrode and the transparent pixel electrode. A rubbing direction for aligning the liquid crystal layer is within 5° with respect to a direction of the gate line to remove a light shielding region above the data line, one end of the transparent common electrode is arranged between the data line and the transparent pixel electrode, and a distance between the transparent common electrode and the transparent pixel electrode is regulated with respect to the data line. | 10-06-2011 |
Hyeon Soo Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110159681 | Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming tunnel insulating patterns to expose portions of the semiconductor substrate by removing portions of the tunnel insulating layer formed over isolation regions of the semiconductor substrate, forming a first conductive layer of single crystalline material over the tunnel insulating patterns and exposed portions of the semiconductor substrate, and forming a second conductive layer over the first conductive layer. | 06-30-2011 |
| 20120199938 | Semiconductor Memory Device and Method of Manufacturing the same - A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern. | 08-09-2012 |
Hyung Hwan Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100159683 | Method for Fabricating Semiconductor Device Having Recess Channel - A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part. | 06-24-2010 |
Hyung Soo Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110292750 | BIT LINE SENSE AMPLIFIER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal. | 12-01-2011 |
Hyun Joo Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120127660 | CYLINDRICAL PACKAGES, ELECTRONIC APPARATUS INCLUDING THE SAME, AND METHODS OF FABRICATING THE SAME - Cylindrical packages are provided. The cylindrical package includes a cylindrical substrate having a hollow region therein and at least one semiconductor chip mounted on an outer circumference of the cylindrical substrate. Related electronic products and related fabrication methods are also provided. | 05-24-2012 |
Hyun Phill Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090093097 | Method for Manufacturing Dual Gate in Semiconductor Device - Provided is a method for manufacturing a dual gate in a semiconductor device. The method includes forming a gate insulating layer and a gate conductive layer on a semiconductor substrate, forming a diffusion barrier layer on the gate conductive layer, forming a barrier metal layer on the diffusion barrier layer, depositing a first gate metal layer on the barrier metal layer, forming a metal nitride barrier layer on a surface of the first gate metal layer by supplying nitrogen (N2) plasma on the first gate metal layer, forming a second gate metal layer on the metal nitride barrier layer, and forming a hard mask layer on the second gate metal layer. | 04-09-2009 |
Hyun Seok Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
Jaepil Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120061859 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULANT CONTAINMENT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming layers having non-horizontal strip patterns and non-vertical strip patterns over the substrate; mounting an integrated circuit device on the substrate adjacent the non-horizontal strip patterns and the non-vertical strip patterns; and applying an encapsulation over the integrated circuit device, the encapsulation restricted by the layers to prevent the encapsulation from reaching an edge of the substrate. | 03-15-2012 |
Ja-Yong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090263967 | Method of forming noble metal layer using ozone reaction gas - A noble metal layer is formed using ozone (O | 10-22-2009 |
Jeen-Gee Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120191863 | PRIVATE MULTIMEDIA CONTENTS BROADCASTING EQUIPMENT WHICH USES ISM RADIO FREQUENCY BAND OR U-NII 5GHz RADIO FREQUENCY BAND, PRIVATE MULTIMEDIA CONTENTS BROADCASTING SYSTEM AND METHOD THEREOF - An individual multimedia contents broadcasting equipment is disclosed, which includes an individual broadcast process unit which provides a private IP through a DHCP (Dynamic Host Configuration Protocol) to a receiving terminal, which requests a connection, and makes a connection of the receiving terminal through a radio network, and transmits a broadcast content to the connected receiving terminal; and a radio communication unit which forms a radio network and communicates data with the connected receiving terminal through the radio network. | 07-26-2012 |
Jeong Soo Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100090791 | Fuse of Semiconductor Memory Device - A fuse used in a semiconductor memory device. The fuse is formed with a “X” shape where one circuit may be connected simultaneously to a plurality of other circuits. As a result, a fuse region is reduced, and the cutting number is also decreased, thereby lowering the possibility of defects resulting from cutting errors. | 04-15-2010 |
| 20100096722 | Fuse in a Semiconductor Device and Method for Fabricating the Same - The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed. As a result, the oxidation of the barrier metal layer is inhibited to improve characteristics of the device. | 04-22-2010 |
Jin-Chul Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120124302 | SOLID STATE STORAGE SYSTEM FOR UNIFORMLY USING MEMORY AREA AND METHOD CONTROLLING THE SAME - A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not. | 05-17-2012 |
Jingwan Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100025835 | INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM - An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive. | 02-04-2010 |
Jin-Woong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090124082 | SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME - A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO | 05-14-2009 |
Jong Il Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110018057 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A manufacturing method of a semiconductor device comprises forming a semiconductor substrate including an active region and an element isolation film, forming a first recess on the semiconductor substrate, forming an oxide film on a sidewall of the first recess, forming a second recess by etching a lower part of the first recess, and forming a gate in a lower part of the second recess. | 01-27-2011 |
Jong Su Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120068239 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR, MEMORY CELL ARRAY HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 03-22-2012 |
Joosang Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090273094 | INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM - An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate. | 11-05-2009 |
Jum Soo Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090129168 | METHOD OF OPERATING A FLASH MEMEORY DEVICE - A method of operating a flash memory device wherein the width of threshold voltage distribution of memory cells is adjusted by setting different conditions of a program operation in accordance with levels of threshold voltages of the memory cells. As a result, width of the threshold voltage distribution of memory cells may be narrowed. | 05-21-2009 |
| 20100295133 | Resistor of Semiconductor Device and Method of Forming the Same - The resistor of a semiconductor device comprises a semiconductor substrate comprising isolation layers and active regions, a gate insulating layer and a first polysilicon layer formed over the active region, a second polysilicon layer separated into a first pattern formed on the isolation layer, and a second pattern formed over the first polysilicon layer and higher than the first pattern, a first interlayer dielectric layer covering the first pattern over the isolation layer, a second interlayer dielectric layer formed over the first interlayer dielectric layer, contact holes exposing the first pattern in the first and second interlayer dielectric layers, and contact plugs filling the respective contact holes and coupled to the first pattern. | 11-25-2010 |
Ki Bum Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120032342 | SEMICONDUCTOR PACKAGE FOR SELECTING SEMICONDUCTOR CHIP FROM A CHIP STACK - A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type. | 02-09-2012 |
Ki Han Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120044002 | SEMICONDUCTOR APPARATUS AND DLL CIRCUIT USING THE SAME - A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal. | 02-23-2012 |
| 20120194233 | DEVICE CHARACTERISTIC COMPENSATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage. | 08-02-2012 |
| 20120212268 | PHASE CONTROL CIRCUIT - A phase control circuit includes a first duty cycle correction circuit configured to correct a duty cycle of a clock signal; a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit; and a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop, wherein the first duty cycle correction circuit and the second duty cycle correction circuit are selectively activated depending upon an operating condition. | 08-23-2012 |
Ki Ho Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110267140 | IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured to activate a voltage detection signal according to a level of a power supply voltage; a multiplexing unit configured to select and output the reference voltage or the first converted voltage in response to the detection signal; and a second calibration unit configured to compare a second converted voltage obtained by converting a second calibration signal with the level of the output signal of the multiplexing unit and vary the second calibration signal. | 11-03-2011 |
| 20120081988 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR SYSTEM - A semiconductor circuit includes a data driving circuit configured to change a slew rate in response to a control signal and drive data at a changed slew rate, a core/peripheral circuit block configured to provide the data to the data driving circuit, and a channel/memory module information setting unit configured to set the control signal according to channel/memory module information. | 04-05-2012 |
Kilho Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110121395 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device includes protection device includes: a high voltage P well formed in a semiconductor substrate, an N-drift region formed in the high voltage P well, an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region, a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region, a buffer N-ballistic region surrounding the buffer N+ diffusion region, an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region, a cathode N+ diffusion region and a cathode P+ diffusion region formed in the high voltage P well and separated a predetermined distance from the N-drift region, a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region, and a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region. | 05-26-2011 |
| 20110169093 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device is a double diffused drain N-type MOSFET (DDDNMOS) ESD protection device, in which a gate, a source region and a well-pickup region are connected to a ground terminal and a drain region is connected to a power terminal or individual input/output terminals. The ESD protection device includes a first conductive type well region formed in a semiconductor substrate, a gate formed to on the semiconductor substrate, a second conductive type source region and a drain region formed in the well region at opposite sides of the gate, a first conductive type well-pickup region formed at one side of the source region, a first conductive type pocket region formed in the well region to surround the source region, a second conductive type drain drift region formed in the well region to surround the drain region, and a first conductive type divot region formed in the drain drift region between a side surface of the gate and the drain region. | 07-14-2011 |
| 20120098046 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device is provided. The ESD protection device includes a first group of electrostatic discharge protection devices connected to a first terminal and including at least one of an LORGGR and an HORGGR, and a second group of electrostatic discharge protection devices connected in series to the first group of electrostatic discharge protection devices and a second terminal and including at least one of a GGNMOS, a GGPMOS and a diode. | 04-26-2012 |
Kil Ho Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100301418 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - Disclosed is an electrostatic discharge protection device that overcomes problems of an LVTNR device by serially connecting a diode to the LVTNR device and coupling a gate of a MOSFET structure thereto. The electrostatic discharge protection device of the present invention includes a diode comprising N well/P | 12-02-2010 |
| 20110013325 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - Disclosed is an improved electrostatic discharge protection device that can effectively cope with electrostatic stress of a microchip operating at high voltage. The ESD protection device includes at least one gate coupled NMOS (GCNMOS) having a gate connected to a drain via a capacitor disposed between the gate and the drain and connected to a source and a well to pick-up via a resistor, and devices for low or medium voltage operation of 6V or less connected in series to the gate coupled NMOS (GCNMOS). | 01-20-2011 |
Kwan Dong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110291722 | PHASE CORRECTION CIRCUIT - A phase correction circuit includes a skew detection unit configured to generate first skew detection signals and second skew detection signals by comparing multi-phase signals with one another, a phase control signal generation unit configured to generate a plurality of phase control signals by combining the first skew detection signals with the second skew detection signals, and a phase adjustment unit configured to delay the multi-phase signals by delay time corresponding to the plurality of the phase control signals. | 12-01-2011 |
| 20120154057 | OSCILLATION CIRCUIT OF SEMICONDUCTOR APPARATUS - An oscillation circuit of a semiconductor apparatus includes a first level regulation unit configured to regulate an output voltage at an output node according to a difference between a reference voltage and the output voltage, and a second level regulation unit coupled between a power supply voltage terminal and a source voltage terminal. | 06-21-2012 |
Mi Jung Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120140544 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING THE SAME - A semiconductor memory apparatus includes a resistive memory cell configured to be applied with a command voltage pulse with a different voltage level, depending upon an input command, and a feedback unit coupled between one end and the other end of the resistive memory cell, and configured to detect whether an amount of current which passes through the resistive memory cell reaches a target level and selectively form a pull-down current path for limiting an amount of current which the resistive memory cell passes, wherein the feedback unit controls the target level according to the command voltage pulse. | 06-07-2012 |
Mincheol Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120042940 | THIN FILM SOLAR CELLS AND METHOD OF MANUFACTURING THE SAME - A thin film solar cell comprises a substrate, an inorganic layer disposed on the substrate and having a plurality of unevenness, a first electrode disposed on the inorganic layer and having a plurality of second unevenness, an absorbing layer disposed on the first electrode, and a second electrode disposed on the absorbing layer. | 02-23-2012 |
Min Cheol Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100134448 | Liquid Crystal Display Device with Touch Screen Function - A liquid crystal display (LCD) device with a touch screen function is provided. The LCD device includes a liquid crystal panel layer including a liquid crystal layer filled between first and second substrates, and a touch panel layer which is formed on the first substrate, includes at least one phase compensating means stacked therein, and detects a contact point when an upper electrode and a lower electrode come into contact with each other due to external pressure, wherein the phase compensating means is patterned so that the upper electrode and the lower electrode are able to contact each other, and thus outdoor visibility and viewing angle characteristics can be effectively improved. | 06-03-2010 |
| 20110259407 | SOLAR CELL INCLUDING MICROLENS AND METHOD OF FABRICATING THE SAME - Disclosed is a method of fabricating a microlens. The method includes forming a self assembly monolayer having a strong hydrophobicity on a substrate; forming a plurality of ink droplets on the self assembly monolayer by jetting a transparent ink using an inkjet apparatus, the transparent ink including a first solvent having a first boiling point, a second solvent having a second boiling point lower than the first boiling point and a silicon oxide (SiOx) solid material dispersed in the first and second solvents; and drying the plurality of ink droplets. | 10-27-2011 |
Minseok Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090243884 | METHOD FOR DISPLAYING TRAFFIC INFORMATION USING PALETTE BASED IMAGE AND DISPLAY APPARATUS USING THE SAME - A method and apparatus to display road information are provided. The method includes receiving traffic information, and displaying an image region corresponding to a link identification (ID) by a palette color corresponding to the traffic information on the basis of the received traffic information. | 10-01-2009 |
Min Su Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100328980 | MULTI-CHIP MEMORY DEVICE - A multi-chip memory device includes a number of chips and a control circuit included in each of the chips and configured to generate an internal chip enable signal in response to set data stored therein and an external chip enable signal | 12-30-2010 |
| 20120057419 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes an address controller for storing fail column addresses and sequentially outputting the fail column addresses while a first control signal is activated and a control logic for performing control so that data indicating a program pass is inputted to each of main page buffers associated with the respective fail column addresses outputted from the address controller while the first control signal is activated. | 03-08-2012 |
Moo Jong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110085121 | Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same - Provided is a fringe field switching (FFS) mode liquid crystal display device (LCD) and a method of fabricating the same that are capable of effectively improving image quality by reducing loads of gate lines and data lines and increasing a conventional storage capacitance. | 04-14-2011 |
Nam-Kyeong Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080298127 | Method of Reading Flash Memory Device for Depressing Read Disturb - Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage. | 12-04-2008 |
| 20090161432 | FLASH MEMORY DEVICE AND OPERATING METHOD THEREOF - A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal. | 06-25-2009 |
| 20090269895 | Method of Manufacturing Non-Volatile Memory Device - Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer. | 10-29-2009 |
| 20110070706 | Method for forming NAND typed memory device - A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors. | 03-24-2011 |
| 20110171797 | NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings. | 07-14-2011 |
| 20120008395 | Nonvolatile Memory Device and Method of Operating the Same - A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage. | 01-12-2012 |
Se Hyun Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090004810 | Method of Fabricating Memory Device - Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height of the first hard mask pattern and the first SNC plug, to increase a top width of the first hard mask pattern, and to reduce a top width of the first SNC plug. The method also includes forming a second hard mask pattern on the first hard mask pattern, and forming a second SNC plug between the second hard mask patterns. | 01-01-2009 |
| 20100200948 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess. | 08-12-2010 |
| 20120080746 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess. | 04-05-2012 |
Seok Su Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090026585 | Semiconductor Device and Method for Manufacturing the same - A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on a side of the first insulating layer in the scribe region; a metallization wiring electrically connected with the substrate via the metal contact plug; and a second insulating layer and a protective layer formed over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region. | 01-29-2009 |
Sook Kyung Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090201728 | Erase Method of Flash Memory Device - Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation. | 08-13-2009 |
| 20090207660 | PROGRAM METHOD OF FLASH MEMORY DEVICE - Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation. | 08-20-2009 |
Su Ho Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090111255 | METHOD FOR FABRICATING TRANSISTOR IN SEMICONDUCTOR DEVICE - Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench. | 04-30-2009 |
Sung Choul Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100124935 | MOBILE COMMUNICATION SYSTEM AND METHOD FOR CAPTURING INFORMATION OF OTHER MOBILE COMMUNICATION TERMINALS - A mobile communication system and a method for capturing information of other mobile communication terminals located within a distance from the user's mobile communication terminal may include a first mobile communication terminal for transmitting capture signal, location information and identification information; the second mobile communication terminals for transmitting location information and identification information of the second mobile communication terminals; and a base station for transmitting the GPS driving signal to the second mobile communication terminals and capturing information of the second mobile communication terminals. | 05-20-2010 |
| 20110059753 | MOBILE COMMUNICATION SYSTEM AND METHOD FOR CAPTURING INFORMATION OF OTHER MOBILE COMMUNICATION TERMINALS - A mobile communication system and a method for capturing information of other mobile communication terminals located within a distance from the user's mobile communication terminal may include a first mobile communication terminal for transmitting capture signal, location information and identification information; the second mobile communication terminals for transmitting location information and identification information of the second mobile communication terminals; and a base station for transmitting the GPS driving signal to the second mobile communication terminals and capturing information of the second mobile communication terminals. | 03-10-2011 |
Sung Wook Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120140584 | SEMICONDUCTOR SYSTEM, SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR INPUT/OUTPUT OF DATA USING THE SAME - A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller. | 06-07-2012 |
Woo Jin Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090122461 | CAPACITOR FOR A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof. | 05-14-2009 |
Yang Hee Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
Yong Ju Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110241726 | ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals. | 10-06-2011 |
| 20110267124 | CLOCK SIGNAL DUTY CORRECTION CIRCUIT - A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal. | 11-03-2011 |
Yongki Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110051528 | Dynamic Semiconductor Memory With Improved Refresh Mechanism - Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed. | 03-03-2011 |
Yong Mi Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120044780 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data. | 02-23-2012 |
| 20120081100 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system. | 04-05-2012 |
Young Bog Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100197110 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved. | 08-05-2010 |
Young Deuk Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090001516 | Semiconductor device and method of fabricating the same - A method of fabricating a semiconductor device includes forming an interlayer insulating pattern over a semiconductor substrate. The interlayer insulating pattern defines a plurality of storage node regions. A lining conductive film is formed over the interlayer insulating pattern including the storage node region. A capping insulating film is formed over the lining conductive film. The capping insulating film over the interlayer insulating film and the lining conductive film are selectively etched between two neighboring storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess. The capping insulating film and the lining conductive film is shaped to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode. A supporting pattern is formed to fill the recess. The capping insulating film and the interlayer insulating pattern are removed to expose the lower storage node. | 01-01-2009 |
Young Seung Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110159676 | FABRICATING LOW CONTACT RESISTANCE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE - A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber. | 06-30-2011 |
Young Won Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
Yu Hwan Kim, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120154020 | STACK PACKAGE AND METHOD FOR SELECTING CHIP IN STACK PACKAGE - A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals. | 06-21-2012 |