Kim, Hwasung-City
Bo Geun Kim, Hwasung-City KR
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20130329497 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 12-12-2013 |
Bum-Suk Kim, Hwasung-City KR
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20100065896 | Image sensor including a pixel cell having an epitaxial layer, system having the same, and method of forming a pixel cell - A pixel cell includes a substrate, an epitaxial layer, and a photo converting device in the epitaxial layer. The epitaxial layer has a doping concentration profile of embossing shape, and includes a plurality of layers that are stacked on the substrate. The photo converting device does not include a neutral region that has a constant potential in the vertical direction. Therefore, the image sensor including the pixel cell has high quantization efficiency, and a crosstalk between photo-converting devices is decreased. | 03-18-2010 |
Do-Gwan Kim, Hwasung-City KR
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20140252750 | KNEE AIRBAG FOR VEHICLE AND FOLDING METHOD THEREOF - A method of folding a knee airbag includes folding a lower portion of the knee airbag perpendicularly to a vertical central axis so that a lower end of the knee airbag is placed on the front panel of the knee airbag, individually folding both sides of the knee airbag toward the vertical central axis, and rolling an upper end portion of the knee airbag toward the lower portion of the knee airbag. The lower portion of the folded knee airbag is rapidly deployed toward the leg of an occupant in the initial deployment of the knee airbag, thereby minimizing time to ensure the minimum space between the instrument panel and the leg of the occupant and rapidly confining the leg of the occupant. | 09-11-2014 |
Hwa-Sung Kim, Hwasung-City KR
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20150107617 | METHOD OF CLEANING PHOTOMASK - A method of cleaning a photomask, the method including placing the photomask in a chamber, the photomask including a mask substrate and a reflective layer, a capping layer, and a light absorbing layer pattern stacked on the mask substrate, and wherein the photomask has contaminants thereon; supplying a gas into the chamber such that the gas does not react with the capping layer or reacts with the capping layer to form an anti-oxidant layer; ionizing the gas by irradiating an inside of the chamber with an energy beam such that the contaminants react with the ionized gas to be converted to a by-product; and removing the by-product from the chamber. | 04-23-2015 |
Hyongsoo Kim, Hwasung-City KR
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20130277802 | INTEGRATED CIRCUIT DEVICES WITH CAPACITOR AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer. | 10-24-2013 |
Hyong-Soo Kim, Hwasung-City KR
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20130230961 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes. | 09-05-2013 |
Hyoung-Rae Kim, Hwasung-City KR
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20080272846 | Adaptive biasing input stage and amplifiers including the same - An adaptive biasing input stage includes pairs of differentially coupled amplifying and sensing field effect transistors having gates with differential inputs applied thereon. In addition, a static current source is coupled to sources of the amplifying and sensing field effect transistors at a predetermined node. Also, current mirrors are coupled to the sensing field effect transistors for forming loop mechanisms for increasing the current through the predetermined node when the differential inputs have a non-zero difference. | 11-06-2008 |
20080316154 | Apparatus and method for generating VCOM voltage in display device - An apparatus for generating a VCOM voltage in a display device includes first and second buffer amplifiers and a charge pump. The first buffer amplifier is biased with high and low rail voltages for generating the VCOM voltage. The second buffer amplifier generates the high rail voltage at an output node not connected to an external capacitor. The charge pump generates the low rail voltage by charge pumping directly from an external power supply voltage. Alternatively, a charge pump and a comparator are used for generating the VCOM voltage at an output of the charge pump. The comparator generates a charge pump control signal from comparing the VCOM voltage with a reference voltage. | 12-25-2008 |
Ik Soo Kim, Hwasung-City KR
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20100129995 | METHOD OF FORMING VARIABLE RESISTANCE MEMORY DEVICE - A method of forming a variable resistance memory device includes forming an opening in an insulating layer, and forming a variable resistance layer by filling the opening with an antimony rich antimony-tellurium compound. | 05-27-2010 |
Jae Choon Kim, Hwasung-City KR
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20120133427 | Semiconductor Devices And Methods Of Controlling Temperature Thereof - An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device. | 05-31-2012 |
20140247859 | SEMICONDUCTOR PACKAGE AND METHOD OF ESTIMATING SURFACE TEMPERATURE OF SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip. | 09-04-2014 |
Jichul Kim, Hwasung-City KR
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20140247859 | SEMICONDUCTOR PACKAGE AND METHOD OF ESTIMATING SURFACE TEMPERATURE OF SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip. | 09-04-2014 |
Ji Hun Kim, Hwasung-City KR
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20160141367 | SEMICONDUCTOR DEVICES INCLUDING CHANNEL DOPANT LAYER - A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device. | 05-19-2016 |
Jingyun Kim, Hwasung-City KR
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20150311214 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures. | 10-29-2015 |
Jung Hoon Kim, Hwasung-City KR
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20140009295 | LIGHTING SYSTEM FOR LIGHT EMITTING DIODE HAVING GAS DETECTION FUNCTION - A light emitting diode (LED) lighting system having a gas detection function may be used not only for lighting but also for detection of volatile organic compounds (VOCs) causing the sick house syndrome at home and other odorless and colorless non-combustible gas harmful to a human body. The LED lighting system may be used as an optical sensor showing with the fast response time and high sensitivity with respect to an environment harmful to a human body. In addition, since the presence of gas can be easily detected through a change of color in comparison to sound alarms for fire and gas contamination, emergency situations can be effectively handled. | 01-09-2014 |
Ki Joon Kim, Hwasung-City KR
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20130221417 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages. | 08-29-2013 |
Ki-Nam Kim, Hwasung-City KR
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20100059805 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an active region and an isolation region. A gate structure is provided on the semiconductor device. First and second impurity regions are provided in the substrate on both sides of the gate structure. A pad electrode is provided to contact the first impurity region. Because the pad electrode is provided on the first impurity region of the semiconductor device, the contact plug does not directly contact the active region. Accordingly, failures caused by damage to the active region may be prevented. | 03-11-2010 |
Kyoung Sun Kim, Hwasung-City KR
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20130154034 | METHOD AND SYSTEM FOR SETTING A PINNED LAYER IN A MAGNETIC TUNNELING JUNCTION - A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer. | 06-20-2013 |
Min-Wook Kim, Hwasung-City KR
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20130117566 | MEMORY SYSTEM - A memory system comprises: a memory device including an authentication data area storing authentication unit information and a verification value, and a contents data area storing contents; and a host device configured to receive the authentication unit information and the verification value from the memory device, and perform secure authentication of the memory device based on whether a result of decoding the verification value is equal to the authentication unit information. | 05-09-2013 |
Nam-Gun Kim, Hwasung-City KR
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20100081286 | Method of etching carbon-containing layer, method of forming contact hole using the same, and method of manufacturing semiconductor device using the same - A method of etching a carbon-containing layer, a method of forming a contact hole using the same, and a method of manufacturing a semiconductor device using the same, the method of etching a carbon-containing layer including forming a capping layer pattern on a carbon-containing layer to expose a portion of the carbon-containing layer, and plasma etching the exposed portion of the carbon-containing layer using an etching gas, wherein the etching gas includes oxygen gas and an inert gas, the inert gas being xenon gas or a gas mixture of xenon gas and argon gas. | 04-01-2010 |
Paul Kim, Hwasung-City KR
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20100264968 | DELAY LOCKED LOOP AND METHOD OF DRIVING DELAY LOCKED LOOP - Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal. | 10-21-2010 |
Sangwon Kim, Hwasung-City KR
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20150123290 | SEMICONDUCTOR PACKAGES HAVING TRENCH-SHAPED OPENING AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package, and a plurality of connection terminals electrically connecting the lower and upper packages. The lower package may include a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer provided on the lower package substrate to mold the lower semiconductor chip. The lower mold layer may have a trench-shaped first opening through which the lower package substrate is exposed in a substantially line shape. The connection terminals may be electrically connected to the lower package substrate exposed by the first opening and be not in contact with the lower mold layer. | 05-07-2015 |
Seonggun Kim, Hwasung-City KR
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20130262738 | PAGE REPLACEMENT METHOD AND MEMORY SYSTEM USING THE SAME - A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory. | 10-03-2013 |
Yang-Ki Kim, Hwasung-City KR
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20110047319 | Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems - A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device. | 02-24-2011 |
Yi-Tae Kim, Hwasung-City KR
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20100065896 | Image sensor including a pixel cell having an epitaxial layer, system having the same, and method of forming a pixel cell - A pixel cell includes a substrate, an epitaxial layer, and a photo converting device in the epitaxial layer. The epitaxial layer has a doping concentration profile of embossing shape, and includes a plurality of layers that are stacked on the substrate. The photo converting device does not include a neutral region that has a constant potential in the vertical direction. Therefore, the image sensor including the pixel cell has high quantization efficiency, and a crosstalk between photo-converting devices is decreased. | 03-18-2010 |
Yonghoon Kim, Hwasung-City KR
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20130214396 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a first package including a first wiring board and at least one first semiconductor chip mounted on the first wiring board, a second package stacked on the first package. The second package includes a second wiring board and at least one second semiconductor chip mounted on the second wiring board. The semiconductor package further includes at least one connection terminal connecting a plurality of signal lines of the first and second wiring boards, respectively, with each other. The semiconductor package further includes at least one ground terminal connecting a plurality of ground lines of the first and second wiring boards, respectively, with each other, and includes a side surface, and a shielding member covering a top surface and a side surface of a structure including the first and second packages and the shielding member is disposed on the at least one ground terminal. | 08-22-2013 |
Young-Ja Kim, Hwasung-City KR
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20130270696 | SEMICONDUCTOR MEMORY MODULES AND METHODS OF FABRICATING THE SAME - The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon. | 10-17-2013 |
20140248743 | SEMICONDUCTOR MEMORY MODULES AND METHODS OF FABRICATING THE SAME - The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon. | 09-04-2014 |
Youngwook Kim, Hwasung-City KR
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20150098275 | FLASH MEMORY BASED ON STORAGE DEVICES AND METHODS OF OPERATION - A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse width of the resulting cycle-controlled data strobe signal is greater than a pulse width of the data strobe signal. | 04-09-2015 |