Patent application number | Description | Published |
20140129568 | REDUCED COMPLEXITY HASHING - Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix. | 05-08-2014 |
20140241358 | PACKET PROCESSING MATCH AND ACTION UNIT WITH A VLIW ACTION ENGINE - An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word. | 08-28-2014 |
20140241359 | PACKET PROCESSING VLIW ACTION UNIT WITH OR-MULTI-PORTED INSTRUCTION MEMORY - An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result. | 08-28-2014 |
20140241361 | PACKET PROCESSING MATCH AND ACTION UNIT WITH CONFIGURABLE MEMORY ALLOCATION - A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory. | 08-28-2014 |
20140241362 | PACKET PROCESSING MATCH AND ACTION UNIT WITH CONFIGURABLE BIT ALLOCATION - A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories. | 08-28-2014 |
20140244966 | PACKET PROCESSING MATCH AND ACTION UNIT WITH STATEFUL ACTIONS - A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory. | 08-28-2014 |
20140328180 | STRUCTURE FOR IMPLEMENTING OPENFLOW ALL GROUP BUCKETS USING EGRESS FLOW TABLE ENTRIES - An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment. | 11-06-2014 |
20140334489 | OPENFLOW MATCH AND ACTION PIPELINE STRUCTURE - An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage. | 11-13-2014 |
Patent application number | Description | Published |
20120127033 | ALIGNMENT SYSTEM - An apparatus for determining alignment of a first subsystem relative to a second subsystem. The apparatus includes a first antenna system for simultaneously transmitting a delta pattern radiation beam at a first frequency and a sum pattern radiation beam at a second frequency. The apparatus also includes a second antenna system for receiving the delta pattern radiation beam at the first frequency and the sum pattern radiation beam at the second frequency. The apparatus also includes a processor to process the received delta pattern radiation beam and sum pattern radiation beam to determine if a predetermined alignment criterion between the first antenna system and the second antenna system is satisfied. | 05-24-2012 |
20130321205 | Method And Apparatus For Analyzing A System Design Having A Phased Array Antenna - Disclosed subject matter is directed to techniques and systems for analyzing a system design having a phase array antenna. In at least one implementation, component models of individual components of the phased array antenna may be provided. The component models may be arranged as a multi-dimensional lookup table (LUT) in some embodiments. A single-channel model of antenna performance may be synthesized for the system design based on the component models. An analysis of the performance of the system design may then be performed using the single-channel model of antenna performance. | 12-05-2013 |
20150276920 | DETECTION OF CONCEALED OBJECT ON A BODY USING RADIO FREQUENCY SIGNATURES ON FREQUENCIES AND POLARIZATIONS - A method for detecting a concealed object in a target comprising a body and the concealed object, the method including emitting, by an emitter, radio frequency (RF) energy toward a direction of the target, receiving, by a receiver, a scattered RF energy reflected from the target, generating, by the receiver, a signal corresponding to the received scattered RF energy, comparing, by a processor, the signal with a plurality of stored RF scattering signatures, each of the RF scattering signatures being associated with an object of interest, and detecting, by the processor, the concealed object when the signal matches one of plurality of RF scattering signatures. | 10-01-2015 |