Patent application number | Description | Published |
20120173598 | APPARATUS AND METHOD FOR DIVISION OF A GALOIS FIELD BINARY POLYNOMIAL - An apparatus and method for processing a division of a binary polynomial are provided. The apparatus includes a plurality of exclusive OR (XOR) operators that may perform a selective XOR operation with respect to a conditional bit of a dividend polynomial. The plurality of XOR operators may perform selective XOR operations in parallel and accordingly, a division of a binary polynomial may be rapidly performed. | 07-05-2012 |
20120288039 | APPARATUS AND METHOD FOR SOFT DEMAPPING - Provided are a soft demapping apparatus and method that may cancel interference included in a rotated quadrature amplitude modulation (QAM) signal, using at least one interference cancellation unit, and may perform one-dimensional (1D) soft demapping of the interference-cancelled rotated QAM signal. | 11-15-2012 |
20120307942 | APPARATUS AND METHOD FOR SOFT DEMAPPING - Provided is a soft demapping apparatus that may detect a log likelihood ratio (LLR) value of a quadrature amplitude modulation (QAM) signal, using a shifted table scheme, may designate a sub-region of the QAM signal corresponding to bit information that is obtained by decoding the LLR value, and may calculate an LLR value of other bit information included in the designated sub-region. | 12-06-2012 |
20130173935 | POWER CONTROL METHOD AND APPARATUS FOR ARRAY PROCESSOR - Provided is an apparatus and method for controlling power to a reconfigurable array processor. The method may determine one or more function units (FUs) as activation function units (FUs) and deactivation FUs among a plurality of FUs included in the reconfigurable array processor. The processor may interrupt power supplied to the deactivation FUs. | 07-04-2013 |
20140254727 | METHOD AND APPARATUS FOR LATTICE REDUCTION WITH REDUCED COMPUTATIONAL COMPLEXITY - Provided is a method and apparatus for lattice reduction with reduced computational complexity. The apparatus and method include calculating an R matrix using sorted QR decomposition, and conducting an R-value test using an R-value based on diagonal elements of the R matrix and a threshold value. The R matrix is an upper triangular matrix. The apparatus and method further execute a loop comprising a size reduction and a conditional update of a basis vector corresponding to a column element of the R matrix in response to the R-value being greater than or equal to the threshold value. The apparatus and method conduct another R-value test based on the R matrix comprising the updated basis vector in response to the basis vector being updated. | 09-11-2014 |
20140270014 | METHOD AND APPARATUS FOR PERFORMING SOFT DEMAPPING IN ROTATED QUADRATURE AMPLITUDE MODULATION (QAM) BASED COMMUNICATION SYSTEM - A soft demapping apparatus and method thereof includes a pre-processing unit to pre-process a reception signal obtained from a symbol representing bits. A candidate selection unit selects two candidates from among constellation points included in a constellation for each of the bits. A distance calculation unit calculates a Euclidean distance between the reception signal and the two candidates. A log-likelihood ratio (LLR) calculation unit calculates an LLR with respect to the bits based on the Euclidean distance between the reception signal and the two candidates. | 09-18-2014 |
20150146810 | METHOD AND APPARATUS FOR PERFORMING SOFT DEMAPPING IN ROTATED QUADRATURE AMPLITUDE MODULATION (QAM) BASED COMMUNICATION SYSTEM - A method of performing a soft demapping, includes obtaining a signal from a symbol representing bits that is transmitted from a transmitter, and calculating a gradient of a reference line in a constellation for a bit based on a rotation angle and a channel state of the constellation. The method further includes selecting a candidate for each of lines that corresponds to a logic value of the bit from constellation points included in the constellation based on the signal and the gradient of the reference line, and calculating a log-likelihood ratio (LLR) of the bit based on the signal and the selected candidate for each of the lines. | 05-28-2015 |
20150154144 | METHOD AND APPARATUS FOR PERFORMING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) OPERATION USING PAIRING OF REGISTERS - An apparatus and a method for performing a single instruction multiple data (SIMD) operation using pairing of registers are provided. An example SIMD apparatus includes a first register configured to store first result data generated by dyadic operators, and a second register configured to store second result data generated by the dyadic operators. The first register and the second register may be paired with each other. Examples also include the use of more than two dyadic operators and/or registers, as well as intermediate registers. | 06-04-2015 |