Patent application number | Description | Published |
20080224267 | SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer. | 09-18-2008 |
20080272434 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer. | 11-06-2008 |
20080277646 | Vertical Type Nanotube Semiconductor Device - A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved. | 11-13-2008 |
20090052243 | Method of controlling a memory cell of non-volatile memory device - A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells. | 02-26-2009 |
20090206387 | Non-volatile memory device, method of fabricating the same, and non-volatile semiconductor integrated circuit device, including the same - A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed. | 08-20-2009 |
20090207666 | Methods of Restoring Data in Flash Memory Devices and Related Flash Memory Device Memory Systems - Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages. | 08-20-2009 |
20090213661 | NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS - A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array. | 08-27-2009 |
20090218558 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate. | 09-03-2009 |
20090219758 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 09-03-2009 |
20100002523 | Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same - Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles. | 01-07-2010 |
20100240209 | SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer. | 09-23-2010 |
20100330752 | Methods of Forming One Transistor DRAM Devices - A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body. | 12-30-2010 |
20110032763 | SEMICONDUCTOR DEVICES INCLUDING FIRST AND SECOND BIT LINES - In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line. | 02-10-2011 |
20110133063 | Optical waveguide and coupler apparatus and method of manufacturing the same - Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die. | 06-09-2011 |
20110300683 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate. | 12-08-2011 |
20120039122 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2 | 02-16-2012 |
20130119349 | GRAPHENE TRANSISTOR HAVING AIR GAP, HYBRID TRANSISTOR HAVING THE SAME, AND METHODS OF FABRICATING THE SAME - A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode. | 05-16-2013 |
20130236125 | SOURCE DEVICE AND METHOD FOR SELECTIVELY DISPLAYING AN IMAGE - A method for selective image distribution using a processor includes determining whether an image includes a non-display image layer and a display image layer; and generating, using the processor, a share image by synthesizing the display image layer. A device includes a layer configuring unit to determine whether an image includes a non-display image layer and a display image layer, and a layer synthesizing unit to synthesize the display image layer to generate a share image. | 09-12-2013 |
20140185378 | MULTI-BIT FLASH MEMORY DEVICE AND MEMORY CELL ARRAY - A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits. | 07-03-2014 |
20140293072 | APPARATUS AND METHOD FOR DETERMINING IMAGE DATA - An apparatus for determining image data is disclosed, the apparatus including an image data identifier to evaluate a state change resulting from blocking or opening of a sensor, and identify a stabilized state of image data of the sensor in an opened state, and an image data determiner to receive image data identified to be the stabilized state, and determine the received image data to be image data absent an occurrence of interference between the sensor and another sensor through an integrity assessment of the image data. | 10-02-2014 |