Patent application number | Description | Published |
20100060317 | DATA OUTPUT DEVICE AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A data output device includes a pre-driver unit configured to control a driving force according to an impedance control signal and to drive output data using the driving force. The data output device includes a main-driver unit configured to control an impedance according to pull-up and pull-down resistance control codes having values that correspond to the impedance control signal provided to the pre-driver unit and to drive an output of the pre-driver unit by utilizing the controlled impedance. | 03-11-2010 |
20100061159 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal. | 03-11-2010 |
20100134164 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock, a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock, and a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled. | 06-03-2010 |
20100165750 | DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF - A data input device of a semiconductor memory apparatus includes input means configured to input data; precharge means configured to supply a precharge voltage for converting inputted data to a differential signal; enable means configured to enable the input means and the precharge means to operate; and control means configured to control a current amount of the enable means in a standby mode. | 07-01-2010 |
20120218838 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device. | 08-30-2012 |
20140098620 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device. | 04-10-2014 |
20140380110 | TEST APPARATUS AND OPERATING METHOD THEREOF - A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested. | 12-25-2014 |
20150043289 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad. | 02-12-2015 |