Patent application number | Description | Published |
20080304345 | Semiconductor memory device with reduced number of channels for test operation - A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled. | 12-11-2008 |
20090006731 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages. | 01-01-2009 |
20090067260 | Buffer control circuit of memory device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller. | 03-12-2009 |
20090119419 | Semiconductor memory device with high-speed data transmission capability, system having the same, and method for operating the same - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 05-07-2009 |
20090154271 | Semiconductor memory device and method for testing the same - Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and outputting the data. | 06-18-2009 |
20090261856 | CIRCUIT AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE - A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an external resistor. The calibration circuit also includes a code generation unit configured to generate a calibration code in response to a voltage of the calibration node and a reference voltage, a calibration resistor unit configured to drive the calibration node in response to the calibration code and turn-off when the code generation unit is disabled, and a precharge unit configured to precharge the precharge node to a predetermined voltage level when the code generation unit is disabled. | 10-22-2009 |
20100254200 | Buffer Control Circuit of Memory Device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller. | 10-07-2010 |
20120284470 | SEMICONDUCTOR MEMORY DEVICE WITH HIGH-SPEED DATA TRANSMISSION CAPABILITY, SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SAME - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 11-08-2012 |