Patent application number | Description | Published |
20080304345 | Semiconductor memory device with reduced number of channels for test operation - A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled. | 12-11-2008 |
20090006731 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages. | 01-01-2009 |
20090067260 | Buffer control circuit of memory device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller. | 03-12-2009 |
20090119419 | Semiconductor memory device with high-speed data transmission capability, system having the same, and method for operating the same - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 05-07-2009 |
20090154271 | Semiconductor memory device and method for testing the same - Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and outputting the data. | 06-18-2009 |
20090261856 | CIRCUIT AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE - A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an external resistor. The calibration circuit also includes a code generation unit configured to generate a calibration code in response to a voltage of the calibration node and a reference voltage, a calibration resistor unit configured to drive the calibration node in response to the calibration code and turn-off when the code generation unit is disabled, and a precharge unit configured to precharge the precharge node to a predetermined voltage level when the code generation unit is disabled. | 10-22-2009 |
20100254200 | Buffer Control Circuit of Memory Device - Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller. | 10-07-2010 |
20120284470 | SEMICONDUCTOR MEMORY DEVICE WITH HIGH-SPEED DATA TRANSMISSION CAPABILITY, SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SAME - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 11-08-2012 |
Patent application number | Description | Published |
20100164540 | Semiconductor Memory Device - A semiconductor memory device includes a reference voltage pad for receiving a reference voltage from an external device, a calibration resistor connected to a calibration node where an external resistor is connected to and having a resistor value decided according to a calibration code, and a calibration code generator for generating the calibration code by comparing a voltage of the calibration node and the reference voltage. | 07-01-2010 |
20110128068 | FUSE CIRCUIT AND OPERATION METHOD THEREOF - A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not. | 06-02-2011 |
20110141830 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a sense amplifier configured to sense and amplify data loaded into a bit line pair, a power line equalize signal generation unit configured to generate a power line equalize signal which is activated until the bit line sense amplifier is enabled after a bit line equalize signal is deactivated, a power line equalizing unit configured to supply a precharge voltage to a pull-up power line and a pull-down power line of the bit line sense amplifier when the power line equalize signal is activated, a pull-up driving unit configured to drive the pull-up power line of the bit line sense amplifier to a pull-up voltage, and a pull-down driving unit configured to drive the pull-down power line of the bit line sense amplifier to a pull-down voltage. | 06-16-2011 |
20110156808 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a first voltage generation unit configured to be operated in response to a first power enable signal to generate a first voltage, a level detection unit configured to detect a level of the first voltage, and a second voltage generation unit configured to be operated in response to a level detection value outputted from the level detection unit to generate a second voltage lower than the first voltage. | 06-30-2011 |
20110158012 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank. | 06-30-2011 |
20110235452 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information. | 09-29-2011 |
20110235453 | FUSE CIRCUIT AND REPAIR CONTROL CIRCUIT USING THE SAME - A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between the fuse and the output terminal and configured to separate or connect the fuse from or to the output terminal in response to a control signal. The voltage equalization unit is configured to equalize both ends of the fuse to the same voltage in response to the control signal. The latching unit is configured to latch and output the output terminal driven by the fuse driving unit. | 09-29-2011 |
20120106277 | REFRESH OPERATION CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND REFRESH OPERATION CONTROL METHOD - A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command, and an address counting unit configured to count the refresh command and generate a row address, wherein a word line of the first cell region designated by the row address is activated when the first row active signal is activated, and a word line of the second cell region designated by the row address is activated when the second row active signal is activated. | 05-03-2012 |
20130044553 | INTEGRATED CIRCUIT, SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF THE SYSTEM - A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command. | 02-21-2013 |
20140181456 | MEMORY, MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE MEMORY AND THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY SYSTEM - A memory controller may include a reception unit configured to receive count information on the number of failed addresses in a memory, an address generation unit configured to generate an address having a value between a minimum address value and a maximum address value, wherein the maximum address value is adjusted based on an original maximum value and the count information, and a transmission unit configured to transmit the generated address to the memory. | 06-26-2014 |
20140185396 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND OPERATION METHOD THEREOF - A memory system includes a semiconductor memory including a storage unit configured to store parameter information in response to a test mode signal and to output the stored parameter information in response to a parameter request signal, and a memory controller configured to provide the parameter request signal to the semiconductor memory and receive the parameter information from the semiconductor memory device. | 07-03-2014 |
20140301150 | MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE AND MEMORY SYSTEM - An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write command, and determining whether to perform a program operation, when the program operation is determined to be performed, programming the temporarily-stored fail address into a programmable storage unit, and receiving a precharge command before the programming of the temporarily-stored fail address is completed. | 10-09-2014 |
20150089326 | ADDRESS DETECTION CIRCUIT AND MEMORY INCLUDING THE SAME - An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units. | 03-26-2015 |