Patent application number | Description | Published |
20100052628 | Circuit and Method for Reducing Output Voltage Transients in a Voltage Mode Buck Converter - A voltage control mode buck converter circuit includes a feedback amplifier providing a comparison signal and a storage circuit in communication with the comparison signal to store a storage comparison signal value. The storage circuit stores the operating conditions for the circuit during normal continuous conduction mode operation in response to sensing a load drop for the circuit. A switching circuit locks the feedback amplifier into the stored operating parameters while the converter circuit operates in non-continuous conduction mode. When the circuit transitions back into the continuous conduction operation mode, the feedback amplifier is already operating at conditions that are compatible with a continuous conduction operation mode. | 03-04-2010 |
20120146540 | METHOD AND APPARATUS TO CONTROL LED BRIGHTNESS - Method and apparatus to control LED brightness are disclosed. An example method includes receiving a dimmer control signal; determining a cutoff point of the dimmer control signal; determining the position of a rising edge signal within the dimmer control signal; determining if the rising edge signal occurred before the cutoff point; and outputting an LED brightness signal indicating full brightness when the rising edge signal occurred before the cutoff point, and indicating a scaled brightness when the rising edge signal did not occur before the cutoff point. | 06-14-2012 |
20130278328 | POWER TRANSISTOR PARTIAL CURRENT SENSING FOR HIGH PRECISION APPLICATIONS - A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor. | 10-24-2013 |
20130314002 | DIGITAL PHASE ANGLE DETECTION AND PROCESSING - Apparatus and methods operate to perform digital time sampling of a waveform associated with a rectified alternating current, edge-controlled power signal, whether leading or trailing edge-controlled. A dimming code (DIM code) is generated based upon rising and falling edge zero crossing timing. The DIM code is normalized with respect to an allowable edge control window synchronized with the waveform. A minimally-dimmed waveform results in a maximum DIM code corresponding to a full-scale DAC maximum brightness analog output signal. The DIM code is loaded into a DAC to be converted to an analog brightness signal. The analog brightness signal may be used by a lighting power controller to control the brightness of one or more lighting elements. Accurate and repeatable light intensities independent of dimmer type may result. | 11-28-2013 |
20140021540 | LDMOS SENSE TRANSISTOR STRUCTURE FOR CURRENT SENSING AT HIGH VOLTAGE - An integrated circuit includes a high voltage n-channel MOS power transistor integrated with a high voltage n-channel MOS blocking transistor. The power transistor and the blocking transistor have electrically coupled drain contact regions. In one embodiment, a drain area of the power transistor is separate from a drain area of the blocking transistor. In another embodiment, the drain area of the power transistor is contiguous with the drain area of the blocking transistor. The power transistor and the blocking transistor have drain extensions with drift areas. The power transistor drift area is laterally adjacent to both sides of the blocking transistor drift area. The drift areas are aligned so that breakdown does not occur between the power transistor and the blocking transistor. The body of the blocking transistor is isolated from the substrate. | 01-23-2014 |
20140097818 | PWM CONTROL APPARATUS FOR AVERAGE OUTPUT CURRENT BALANCING IN MULTI-STAGE DC-DC CONVERTERS - Pulse width modulation controller apparatus and techniques are presented for balancing output currents of DC-DC converter stages in a multi-stage DC-DC conversion system in which a reference current is provided according to an input voltage and the value of a connected resistor, and a correction current output signal is generated that represents the difference between an average converter stage load current and the local load current, with the on-time of the PWM output signal being generated by charging a capacitance using a charging current obtained by offsetting the reference current output signal with the correction current output signal. | 04-10-2014 |
20140097881 | BALANCED AUXILIARY ON TIME GENERATOR FOR MULTIPHASE STACKABLE CONSTANT ON TIME CONTROL ARCHITECTURE - A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture. | 04-10-2014 |
Patent application number | Description | Published |
20120036395 | DETECTING DATA-WRITE ERRORS - An embodiment of a data read path includes recovery and decoder circuits. The recovery circuit is operable to recover coded data from a storage medium, and the decoder circuit is operable to detect, in the recovered data, a write error that occurred during a writing of the coded data to the storage medium. For example, such an embodiment may allow detection of a write error that occurred while writing data to a bit-patterned storage medium. | 02-09-2012 |
20120036414 | RENDERING DATA WRITE ERRORS DETECTABLE - An embodiment of a data write path includes encoder and write circuits. The encoder circuit is operable to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is operable to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium. | 02-09-2012 |
20130275714 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 10-17-2013 |
20140036589 | MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES - The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley. | 02-06-2014 |
20140153332 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 06-05-2014 |
20140164867 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION - The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. | 06-12-2014 |
20140208054 | DETERMINING SOFT DATA FOR FRACTIONAL DIGIT MEMORY CELLS - Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping. | 07-24-2014 |
20140208189 | DETERMINING SOFT DATA USING A CLASSIFICATION CODE - Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits. | 07-24-2014 |
20140244964 | DUAL MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted. | 08-28-2014 |
20140351491 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 11-27-2014 |