Patent application number | Description | Published |
20120310022 | Compositions And Methods For Inhibiting Naphthenate Solids Formation From Liquid Hydrocarbons - The present invention relates to a composition and method for inhibiting the formation of naphthenate solids in a liquid hydrocarbon. The method includes contacting a composition including a rosin amine having a formula (I): or (II): where formula (AA): represents a single or double bond; R1, R2 and R5 each independently represent H, alkyl, alkenyl or an alkynyl group each having between one and ten carbon atoms, —(R3O)nR4 wherein R3 is an alkyl group having 1 to 3 carbon atoms and R4 is H, alkyl, alkenyl or an alkynyl group each having between one and ten carbon atoms; n is an integer between 5 and 50; X is a halide, sulphate, phosphate or acetate ion; and a demulsifier intermediate with the liquid hydrocarbon. | 12-06-2012 |
20130210155 | Methods For Selection Of A Naphthenate Solids Inhibitor And Test Kit, And Method For Precipitating Naphthenate Solids - The present invention relates to a method for identifying an inhibitor to the formation of naphthenate solids in a liquid hydrocarbon including contacting a sample of the liquid hydrocarbon with an inhibitor and a buffered aqueous solution, observing the extent of formation of naphthenate solids, if any, the extent of formation of naphthenate solids being indicative of the effectiveness of the inhibitor, and repeating the steps, if necessary, until a suitable inhibitor is identified. The present invention also relates to a method for identifying an inhibitor to the formation of naphthenate scale in a liquid hydrocarbon system as well as test kits for use in the methods. | 08-15-2013 |
Patent application number | Description | Published |
20090282404 | Provisioning of Computer Systems Using Virtual Machines - A provisioning server automatically configures a virtual machine (VM) according to user specifications and then deploys the VM on a physical host. The user may either choose from a list of pre-configured, ready-to-deploy VMs, or he may select which hardware, operating system and application(s) he would like the VM to have. The provisioning server then configures the VM accordingly, if the desired configuration is available, or it applies heuristics to configure a VM that best matches the user's request if it isn't. The invention also includes mechanisms for monitoring the status of VMs and hosts, for migrating VMs between hosts, and for creating a network of VMs. | 11-12-2009 |
20120265959 | SYSTEM AND METHOD FOR CONVERTING A PHYSICAL DISK TO A VIRTUAL DISK - A method for converting a disk of a physical computer into a virtual disk for use by a virtual machine is described. Contents of the disk of the physical computer are copied into an image file, wherein the image file has a different sector-by-sector organization of the contents than the disk but a logically equivalent file system organization. Hardware configuration information from the image file is then extracted, wherein the hardware configuration information relates to hardware of the physical computer and, based on a comparison of the extracted hardware configuration information and a virtual hardware configuration of the virtual machine, hardware-dependent files in the image file are replaced with substitute files that are compatible with the virtual hardware configuration of the virtual machine. | 10-18-2012 |
20130060919 | PROVISIONING OF COMPUTER SYSTEMS USING VIRTUAL MACHINES - A provisioning server automatically configures a virtual machine (VM) according to user specifications and then deploys the VM on a physical host. The user may either choose from a list of pre-configured, ready-to-deploy VMs, or he may select which hardware, operating system and application(s) he would like the VM to have. The provisioning server then configures the VM accordingly, if the desired configuration is available, or it applies heuristics to configure a VM that best matches the user's request if it isn't. The invention also includes mechanisms for monitoring the status of VMs and hosts, for migrating VMs between hosts, and for creating a network of VMs. | 03-07-2013 |
Patent application number | Description | Published |
20120042319 | Scheduling Parallel Data Tasks - A method for allocating parallel, independent, data tasks includes receiving data tasks, each of the data tasks having a penalty function, determining a generic ordering of the data tasks according to the penalty functions, wherein the generic ordering includes solving an aggregate objective function of the penalty functions, the method further including determining a schedule of the data tasks given the generic ordering, which packs the data tasks to be performed. | 02-16-2012 |
20120110047 | Reducing the Response Time of Flexible Highly Data Parallel Tasks - A method for scheduling a data processing job includes receiving the data processing job formed of a plurality of computing units, combining the plurality of computing units into a plurality of sets of tasks, each set including tasks of about equal estimated size, and different sets having different sized tasks, and assigning the tasks to a plurality of processors using a dynamic longest processing time (DLPT) scheme. | 05-03-2012 |
20150074681 | SCHEDULING PARALLEL DATA TASKS - A method for allocating parallel, independent, data tasks includes receiving data tasks, each of the data tasks having a penalty function, determining a generic ordering of the data tasks according to the penalty functions, wherein the generic ordering includes solving an aggregate objective function of the penalty functions, the method further including determining a schedule of the data tasks given the generic ordering, which packs the data tasks to be performed. | 03-12-2015 |
Patent application number | Description | Published |
20100325621 | PARTITIONING OPERATOR FLOW GRAPHS - Techniques for partitioning an operator flow graph are provided. The techniques include receiving source code for a steam processing application, wherein the source code comprises an operator flow graph, wherein the operator flow graph comprises a plurality of operators, receiving profiling data associated with the plurality of operators and one or more processing requirements of the operators, defining a candidate partition as a coalescing of one or more of the operators into one or more sets of processing elements (PEs), using the profiling data to create one or more candidate partitions of the processing elements, using the one or more candidate partitions to choose a desired partitioning of the operator flow graph, and compiling the source code into an executable code based on the desired partitioning. | 12-23-2010 |
20110061060 | Determining Operator Partitioning Constraint Feasibility - Techniques for determining feasibility of a set of one or more operator partitioning constraints are provided. The techniques include receiving one or more sets of operator partitioning constraints, wherein each set of one or more constraints define one or more desired conditions for grouping together of operators into partitions and placing partitions on hosts, wherein each operator is embodied as software that performs a particular function, processing each set of one or more operator partitioning constraints to determine feasibility of each set of one or more operator partitioning constraints, creating and outputting one or more candidate partitions and one or more host placements for each set of feasible partitioning constraints, and creating and outputting a certificate of infeasibility for each set of infeasible partitioning constraints, wherein the certificate of infeasibility outlines one or more reasons for infeasibility. | 03-10-2011 |
20110191759 | Interactive Capacity Planning - Techniques for performing capacity planning for applications running on a computational infrastructure are provided. The techniques include instrumenting an application under development to receive one or more performance metrics under a physical deployment plan, receiving the one or more performance metrics from the computational infrastructure hosting one or more applications that are currently running, using a predictive inference engine to determine how the application under development can be deployed, and using the determination to perform capacity planning for the applications on the computational infrastructure. | 08-04-2011 |
20110258246 | DISTRIBUTED SOLUTIONS FOR LARGE-SCALE RESOURCE ASSIGNMENT TASKS - Distributed data processing of problems representing resource assignment tasks. The problems are modeled as programs, and the programs are partitioned into sub-instances. Those sub-instances are executed in a distributed computing environment. The partitioning reduces communication costs between sub-instances and convergence time for the optimization program. | 10-20-2011 |
20120174110 | AMORTIZING COSTS OF SHARED SCANS - Techniques for scheduling a plurality of jobs sharing input are provided. The techniques include partitioning one or more input datasets into multiple subcomponents, analyzing a plurality of jobs to determine which of the plurality of jobs require scanning of one or more common subcomponents of the one or more input datasets, and scheduling a plurality of jobs that require scanning of one or more common subcomponents of the one or more input datasets, facilitating a single scanning of the one or more common subcomponents to be used as input by each of the plurality of jobs. | 07-05-2012 |
20120304186 | Scheduling Mapreduce Jobs in the Presence of Priority Classes - Techniques for scheduling one or more MapReduce jobs in a presence of one or more priority classes are provided. The techniques include obtaining a preferred ordering for one or more MapReduce jobs, wherein the preferred ordering comprises one or more priority classes, prioritizing the one or more priority classes subject to one or more dynamic minimum slot guarantees for each priority class, and iteratively employing a MapReduce scheduler, once per priority class, in priority class order, to optimize performance of the one or more MapReduce jobs. | 11-29-2012 |
20120304188 | Scheduling Flows in a Multi-Platform Cluster Environment - Techniques for scheduling multiple flows in a multi-platform cluster environment are provided. The techniques include partitioning a cluster into one or more platform containers associated with one or more platforms in the cluster, scheduling one or more flows in each of the one or more platform containers, wherein the one or more flows are created as one or more flow containers, scheduling one or more individual jobs into the one or more flow containers to create a moldable schedule of one or more jobs, flows and platforms, and automatically converting the moldable schedule into a malleable schedule. | 11-29-2012 |
20130031558 | Scheduling Mapreduce Jobs in the Presence of Priority Classes - Techniques for scheduling one or more MapReduce jobs in a presence of one or more priority classes are provided. The techniques include obtaining a preferred ordering for one or more MapReduce jobs, wherein the preferred ordering comprises one or more priority classes, prioritizing the one or more priority classes subject to one or more dynamic minimum slot guarantees for each priority class, and iteratively employing a MapReduce scheduler, once per priority class, in priority class order, to optimize performance of the one or more MapReduce jobs. | 01-31-2013 |
20130031561 | Scheduling Flows in a Multi-Platform Cluster Environment - Techniques for scheduling multiple flows in a multi-platform cluster environment are provided. The techniques include partitioning a cluster into one or more platform containers associated with one or more platforms in the cluster, scheduling one or more flows in each of the one or more platform containers, wherein the one or more flows are created as one or more flow containers, scheduling one or more individual jobs into the one or more flow containers to create a moldable schedule of one or more jobs, flows and platforms, and automatically converting the moldable schedule into a malleable schedule. | 01-31-2013 |
20130151536 | Vertex-Proximity Query Processing - A method, an apparatus and an article of manufacture for processing a random-walk based vertex-proximity query on a graph. The method includes computing at least one vertex cluster and corresponding meta-information from a graph, dynamically updating the clustering and corresponding meta-information upon modification of the graph, and identifying a vertex cluster relevant to at least one query vertex and aggregating corresponding meta-information of the cluster to process the query. | 06-13-2013 |
20130239100 | Partitioning Operator Flow Graphs - Techniques for partitioning an operator flow graph are provided. The techniques include receiving source code for a stream processing application, wherein the source code comprises an operator flow graph, wherein the operator flow graph comprises a plurality of operators, receiving profiling data associated with the plurality of operators and one or more processing requirements of the operators, defining a candidate partition as a coalescing of one or more of the operators into one or more sets of processing elements (PEs), using the profiling data to create one or more candidate partitions of the processing elements, using the one or more candidate partitions to choose a desired partitioning of the operator flow graph, and compiling the source code into an executable code based on the desired partitioning. | 09-12-2013 |
Patent application number | Description | Published |
20110108981 | REDISTRIBUTION LAYER ENHANCEMENT TO IMPROVE RELIABILITY OF WAFER LEVEL PACKAGING - An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP. | 05-12-2011 |
20110233756 | WAFER LEVEL PACKAGING WITH HEAT DISSIPATION - A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the manufacturing process as well as the resulting WLP. | 09-29-2011 |
20130105966 | THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION | 05-02-2013 |
20130161817 | TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES - Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. | 06-27-2013 |
20140131859 | SOLDER FATIGUE ARREST FOR WAFER LEVEL PACKAGE - A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core. | 05-15-2014 |
20140167252 | LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES - Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like. | 06-19-2014 |
20140183747 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 07-03-2014 |
20140252571 | WAFER-LEVEL PACKAGE MITIGATED UNDERCUT - A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the substrate, depositing and patterning a resist layer, depositing a redistribution layer structure, removing the photoresist layer, and dry-etching the metal seed layer. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a substrate, a metal seed layer disposed on the substrate, and a redistribution layer structure formed on the metal seed layer. The metal seed layer is dry-etched so that undercut is mitigated. | 09-11-2014 |
20140264845 | WAFER-LEVEL PACKAGE DEVICE HAVING HIGH-STANDOFF PERIPHERAL SOLDER BUMPS - A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps. | 09-18-2014 |
20150028475 | TECHNIQUE FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES - Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. | 01-29-2015 |
20150325512 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 11-12-2015 |
20160071826 | THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION - An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold. | 03-10-2016 |