Patent application number | Description | Published |
20080270750 | INSTRUCTION-PARALLEL PROCESSOR WITH ZERO-PERFORMANCE-OVERHEAD OPERAND COPY - A processor having a zero-overhead operand copy capability. The processor includes multiple execution units to execute instructions in parallel and multiple register files each associated with one or more of the execution units. The processor further includes circuitry to select either an instruction execution result from a first one of the execution units or content of a register within a first one of the register files associated with the first one of the execution units to be stored within a register within a second one of the register files. | 10-30-2008 |
20080301418 | TRACING COMMAND EXECUTION IN A PARALLEL PROCESSING SYSTEM - Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory. | 12-04-2008 |
20080307207 | DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR - A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes. | 12-11-2008 |
20120011349 | DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR - Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. | 01-12-2012 |
Patent application number | Description | Published |
20140032828 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR COPYING DATA BETWEEN MEMORY LOCATIONS - A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction. | 01-30-2014 |
20140052918 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MANAGING CACHE MISS REQUESTS - A system, method, and computer program product are provided for managing miss requests. In use, a miss request is received at a unified miss handler from one of a plurality of distributed local caches. Additionally, the miss request is managed, utilizing the unified miss handler. | 02-20-2014 |
20140126275 | SYSTEM AND METHOD FOR TUNING A SUPPLY VOLTAGE FOR DATA RETENTION - A processor and a system are provided for tuning a supply voltage for data retention. The contents of data storage circuitry are read and a data verification indication corresponding to the contents is computed. Then, the supply voltage provided to the data storage circuitry is reduced to a low voltage level that is intended to retain the contents of the data storage circuitry. | 05-08-2014 |
20140136778 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING A STORAGE ARRAY - A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (SRAM). Additionally, the storage array is utilized in a multithreaded architecture. | 05-15-2014 |
20140268976 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network. | 09-18-2014 |
20140301134 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network. | 10-09-2014 |