Patent application number | Description | Published |
20090014094 | Methods for Reducing Hexavalent Chromium in Trivalent Chromate Conversion Coatings - The present invention is directed to trivalent chromate conversion coatings for plated metals, and more particularly, to methods for reducing hexavalent chromium in trivalent chromate conversion coatings. In one embodiment, such method includes placing a metal article having a trivalent chromate conversion coating in a reducing solution. The trivalent chromate conversion coating includes hexavalent chromium and the reducing solution including a reducing agent, which reduces the hexavalent chromium so as to reduce or eliminate the hexavalent chromium on the plated metal article. | 01-15-2009 |
20100243716 | Enhanced Connector Cradle Having a Cooling Shell for Preferential Cooling of Wafers - A method, system and apparatus for preferential cooling of an electrical circuit board via a cradle having a cooling shell. An enhanced connector cradle enables the secure and precise placement of a connector on a circuit board by using a cooling component which selectively enables only the connector leads to reach reflow temperature levels. The cradle aligns and securely connects the circuit board to the connector via a comb structure of the cradle to form a single connector unit. Heat is applied to the single connector unit to initiate bond formation. The cradle selectively minimizes the heat to the circuit board and other board components by enabling the circulation of de-ionized water through the cooling component during the heating process. As a result, the cradle restricts reflow temperature levels to the connector leads. The cradle mechanism is removed from the board after the connector is securely bonded to the board. | 09-30-2010 |
20120018666 | METHOD AND SYSTEM FOR ALIGNMENT OF GRAPHITE NANOFIBERS FOR ENHANCED THERMAL INTERFACE MATERIAL PERFORMANCE - The exemplary embodiments of the present invention provide a method and system for aligning graphite nanofibers in a thermal interface material to enhance the thermal interface material performance. The method includes preparing the graphite nanofibers in a herringbone configuration, and dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The method further includes applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. The system includes the graphite nanofibers configured in a herringbone configuration and a means for dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The system further includes a means for applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. | 01-26-2012 |
20120217987 | NON-DESTRUCTIVE DETERMINATION OF THE MOISTURE CONTENT IN AN ELECTRONIC CIRCUIT BOARD USING COMPARISON OF CAPACITANCE MEASUREMENTS ACQUIRED FROM TEST COUPONS, AND DESIGN STRUCTURE/PROCESS THEREFOR - Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated. | 08-30-2012 |
20130020716 | SYSTEM AND METHOD TO PROCESS HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN A THERMAL INTERFACE MATERIAL USED IN 3D CHIP STACKS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. | 01-24-2013 |
20130240250 | CIRCUIT APPARATUS HAVING A ROUNDED DIFFERENTIAL PAIR TRACE - A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace. | 09-19-2013 |
20140070393 | HORIZONTALLY AND VERTICALLY ALIGNED GRAPHITE NANOFIBERS THERMAL INTERFACE MATERIAL FOR USE IN CHIP STACKS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip | 03-13-2014 |
20140205232 | IMPLEMENTING EMBEDDED HYBRID ELECTRICAL-OPTICAL PCB CONSTRUCT - Methods and structures are provided for implementing embedded hybrid electrical-optical printed circuit board (PCB) constructs. The embedded hybrid electrical-optical PCB construct includes electrical channels and optical channels within a single physical PCB layer. The embedded hybrid electrical-optical PCB construct includes an electrically conductive sheet or a copper sheet, and a reflective mesh adhesive layer provided with the electrical channels and optical channels within the single physical PCB layer. | 07-24-2014 |
20140210068 | HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN ETCHED SILICON WAFER TROUGHS FOR ENHANCED THERMAL PERFORMANCE - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad. | 07-31-2014 |