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Keun Soo

Keun Soo Kim, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20110117104MONOCLONAL ANTIBODY SPECIFIC TO ANTHRAX TOXIN - Disclosed is a monoclonal antibody having very high affinity to anthrax toxin and potent toxin-neutralizing activity. Also disclosed are a composition for neutralizing anthrax toxin comprising the antibody and a kit for detecting anthrax toxin.05-19-2011

Keun Soo Kim, Daejeon KR

Patent application numberDescriptionPublished
20080279847Humanized Anti-Tag-72 Monoclonal Antibodies - The present invention relates to humanized antibodies specific to a tumor associated glycoprotein, TAG-72, and anticancer compositions comprising the humanized antibodies. In detail, the present invention relates to a humanized antibody which has enhanced antigen binding affinity by mutating a heavy chain of a humanized antibody PXA/HzK specific for TAG-72, an antibody which is prepared by replacing a light chain of the humanized antibody with a human light chain, and anticancer compositions including the antibodies.11-13-2008
20110117643Recombinant Expression Vector for Animal Cell - The present invention relates to a recombinant expression vector for an animal cell containing a dihydrofolate reductase (DHFR) coding nucleotide sequence operatively linked to a DHFR promoter, to an animal cell line transformed by the vector, and to a method for preparing a target protein using the same. As compared with existing animal cell expression vectors, the vector of the present invention enables an effective screening of a cell line clone in which foreign genes are amplified together with DHFR genes even at a much lower methotrexate concentration. The present invention exhibits excellent effects in cell line preparation as high-productivity cell lines can be ensured in a short time through the use of a lower concentration of methotrexate in the process of protein production cell line establishment.05-19-2011

Keun Soo Kim, Seoul KR

Patent application numberDescriptionPublished
20100101710METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst.04-29-2010
20110209816METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst.09-01-2011
20120132358METHOD FOR REMOVING A CARBONIZATION CATALYST FROM A GRAPHENE SHEET AND METHOD FOR TRANSFERRING THE GRAPHENE SHEET - A method for removing a carbonization catalyst from a graphene sheet, the method includes contacting the carbonization catalyst with a salt solution, which is capable of oxidizing the carbonization catalyst.05-31-2012
20120298396GRAPHENE FIBER, METHOD FOR MANUFACTURING SAME AND USE THEREOF - The present disclosure relates to a manufacturing method of a graphene fiber, a graphene fiber manufactured by the same method, and use thereof. The graphene fiber formed by using graphenes of linear pattern can be applied to various fields such as an electric wire and coaxial cable.11-29-2012

Patent applications by Keun Soo Kim, Seoul KR

Keun Soo Lee, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20100062553Organic Light Emitting Display Device - An organic light emitting display device capable of hermetically sealing a space between a deposition substrate and an encapsulation substrate with inorganic sealing materials is disclosed. One embodiment of the organic light emitting display device includes a first substrate including power supply lines formed on an array, and a circumference of the array, of an organic light emitting diode, and connected to a pad unit through the power pad line to supply a power source to each of the organic light emitting diodes; a second substrate arranged on at least the array of the first substrate; and an inorganic sealing material for sealing an inner space between the first substrate and the second substrate while forming a closed boundary, wherein the inorganic sealing material is not overlapped with a region in which the power supply line is formed.03-11-2010

Keun Soo Park, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20090134519SEMICONDUCTOR DEVICE - Embodiments relate to a semiconductor device. In embodiments, the semiconductor device may include a semiconductor substrate having a first metal line; a pre-metal dielectric (PMD) layer over the first metal line on the semiconductor substrate; a first metal layer formed in a first contact hole in the PMD layer; a second metal layer formed in a second contact hole in the PMD layer; and a second metal line electrically connected to the first and second metal layers, respectively, over the PMD layer, wherein the first and second metal layers are located at prescribed positions and configured to be electrically connected to the first metal line.05-28-2009

Keun Soo Park, Seoul KR

Patent application numberDescriptionPublished
20080209231Contents Encryption Method, System and Method for Providing Contents Through Network Using the Encryption Method - Disclosed are a contents encryption method, and a system and method for providing contents through a network using the contents encryption method. In order to provide contents through the network more securely, at least one piece of contents and corresponding metadata are recursively multi-encrypted at least once, and encrypted data are then provided. In particular, encrypted positions of the contents and corresponding decryption information are expressed as metadata, and the metadata include parameter information on respective encryption tools used for multi-encryption, an order of the applied encryption tools, positions of the encryption tools, and a list of encryption tool substitutes. The metadata are provided when the contents are provided. Therefore, the contents provider and receiver can more safely and systematically manage the metadata including contents decryption information, and multimedia are efficiently protected, managed, and controlled.08-28-2008
20100014666Method and Apparatus for Protecting Scalable Video Coding Contents - Disclosed are a method and apparatus capable of reducing the computational complexity of encryption and decryption by encrypting only data of scalable video coding contents for each coding layer in terms of temporal, spatial, and SNR scalabilities to provide a service for protected scalable video coding contents, and capable of protecting contents by generating and distributing an encryption key for encryption and decryption depending on a class of a contents consumer.01-21-2010

Patent applications by Keun Soo Park, Seoul KR

Keun Soo Song, Icheon-Si KR

Patent application numberDescriptionPublished
20110058441DATA LINE DRIVING CIRCUIT - A data line driving circuit includes: an operation period signal generation unit configured to generate an operation period signal for determining a write period and a read period in response to a read command or a write command; and a read data line driving unit configured to fix a read data line to a first voltage level in response to the operation period signal, the read data line being dedicated to a read operation.03-10-2011
20120195140SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal. The semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input/output modes using the logic levels of the first and second pads.08-02-2012

Keun Soo Song, Ichon-Shi KR

Patent application numberDescriptionPublished
20110267910SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING COLUMN REDUNDANCY FUSE BLOCK - A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting state of the column address fuses, wherein the column redundancy fuse is disposed in the edge area, wherein the fuse blowing determination signal is inputted to a column control block through upper portion of a memory cell array of a corresponding bank.11-03-2011

Keun Soo Song, Ichon KR

Patent application numberDescriptionPublished
20090122632STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.05-14-2009

Keun Soo Song, Kyeongki-Do KR

Patent application numberDescriptionPublished
20090033429Phase locked loop for stably operating in a matter that is insensitive to variation in process, voltage and temperature and method of operating the same - A phase locked loop for stably operating in a matter that is insensitive to variation in PVT and a method of operating the same. The PLL according to the present invention includes a PFD, a charge pump circuit, a loop filter, a VCO, and a peak voltage detector. The PFD compares a phase or frequency of a reference signal with a phase or frequency of an output signal and outputs an up signal or a down signal based on the comparison result. The charge pump circuit generates a pumping current in response to the up signal or the down signal and increases or decreases the pumping current in response to a detection signal. The loop filter outputs control voltage according to the pumping current. The VCO outputs the output signal having a frequency determined based on the control voltage. The peak voltage detector detects the peak value of the control voltage and outputs the detection signal based on the detection result. The PLL detects the peak value of control voltage and controls the operation of a charge pump circuit based on the detection result thereby decreasing the peaking and ringing phenomena of the control voltage and then stably operating in a manner that is insensitive to variation in PVT.02-05-2009

Keun Soo Song, Icheon KR

Patent application numberDescriptionPublished
20110291762INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation.12-01-2011

Keun Soo Yoon, Seoul KR

Patent application numberDescriptionPublished
20130118028FUNCTIONAL SHOE HAVING A CUSHIONING FUNCTION AND AN AIR CIRCULATION FUNCTION - A functional shoe pertains to a cushioning function and an air circulation function, which integrally performs the cushioning function and the air circulation function. The functional shoe includes: an insole (05-16-2013

Keun Soo Yun, Seoul KR

Patent application numberDescriptionPublished
20090248501Calculation method of sales allowance and computer readable recording medium thereof - Disclosed are calculation method of sales allowance and computer readable recording medium thereof that are capable of calculating allowance to be paid to respective members corresponding to each node online in a commodity or service sales method. The method comprises the steps of computing a rate of a ranking of a predetermined subscriber to the number of subscribers included on one line; computing a rate of sales of the predetermined subscriber to the total of sales of respective subscribers included on the one line; computing the rate computed in the step times the rate computed in the step times a sales allowance payment rate of new sales; automatically computing an allowance of the predetermined subscriber by the product of the value computed in the step and a predetermined invariable; and displaying the value computed in the step on the monitor of a computer. Thus, according to the present, it is possible to compute a sales allowance paid to subscribers according to respective steps simply and correctively without manager's complicated computation in case of the generation of new sales by online automatically computing allowances correctively allotted to members included on one line according to a payment rate in a commodity or service sales method.10-01-2009
20100185528METHOD FOR ELECTRONIC COMMERCE USING POINTS, SYSTEM AND RECORDING MEDIUM THEREOF - Embodiments of the present invention relate to a method for electronic commerce, a system, and a recording medium thereof, and more particularly, to a method for electronic commerce using a point on the basis of the grade of a member depending on the position and code of each of a GM member and an SM member on-line, an electronic commerce system, and a recording medium readable by a computer. A method for electronic commerce, an electronic commerce system, and a computer-readable recording medium of embodiments of the present invention have advantages of creating an increase in the number of members having loyalty by enhancing an association relationship between members and providing a higher incentive to a member inducing membership joining and the resultant activation of an on-line enterprise.07-22-2010
20100205051CALCULATION METHOD OF SALES COMMISSION USING TRANSFORMATION COEFFICIENT IN ON-LINE, CALCULATION SYSTEM AND RECORDING MEDIUM THEREOF - Disclosed are a method and a system of calculating a sales commission using a transformation coefficient in on-line by reflecting sales of members receiving sales commissions and new sales of sub-members, and a record medium thereof. Members receive sales commissions based on members' own sales, so that old sub-members as well as new members actively sell commodities. The property of the tree to which the members belong is more increased, so that the members have reliability and affection for a company. The revenue of the members is more increased, and a company attempts to increase sales and members. A company determines sales commissions paid to members at a constant commission payment rate for the sales of the members without being affected by the enlargement of an organization due to the increase of the members and the amount of sales.08-12-2010
20110193313FOLDABLE BICYCLE - Disclosed is a foldable bicycle. The foldable bicycle includes a head frame having a first connection part, a first lower frame integrally formed with the head frame and provided at a terminal end thereof with a second fastening part, a second lower frame provided with a second connection part extending from one side of the perforation hole, a slide member coupled with the second lower frame to slidably move lengthwise along the second lower frame and provided at an upper portion thereof with a third connection part, a saddle frame provided at a lower portion thereof with a third fastening part rotatably coupled with the third connection part, and a horizontal frame provided at one end thereof with a fourth fastening part rotatably coupled with saddle frame, and at the other end thereof with a first fastening part rotatably coupled with a first connection part.08-11-2011
20110218901ON-LINE PRODUCT AUCTION METHOD USING STOCK INDEX AND RECORDING MEDIUM - An online product auction method using stock price indexes is disclosed. A plurality of bidders participates in online auction bidding for a presented product and inputs respective bid numbers. Specific numbers are extracted from two or more indexes which indicate stock prices. A successful bid number is created by combining the extracted numbers in a predetermined sequence. It is determined whether a bid number identical to the successful bid number exists among the bid numbers. If one or more bid numbers identical to the successful bid number exist, an earliest bidder is selected for a successful bidder. If no bid number identical to the successful bid number exists, an earliest bidder, having a bid number which is the closest to the successful bid number, is selected for a successful bidder. Thereafter, a command is output to deliver the corresponding product to the selected bidder.09-08-2011

Patent applications by Keun Soo Yun, Seoul KR

Keun-Soo Jo, Hwaseong-Si KR

Patent application numberDescriptionPublished
20100232196MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE PROVIDING ACTIVE TERMINATION CONTROL - A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.09-16-2010
20110126066MULTI-CHIP MEMORY SYSTEM AND RELATED DATA TRANSFER METHOD - A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.05-26-2011
20120030414NON VOLATILE MEMORY APPARATUS, DATA CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory.02-02-2012

Patent applications by Keun-Soo Jo, Hwaseong-Si KR

Keun-Soo Lee, Suwon-Si KR

Patent application numberDescriptionPublished
20090033597LIGHT EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - A light emitting display and a method of manufacturing the same. The light emitting display includes a substrate, a plurality of first and second signal lines that cross each other on the substrate, a plurality of organic light emitting diodes (OLEDs) coupled between the first signal lines and the second signal lines, a power source supply line for supplying a power source voltage to the OLEDs, and a plurality of inspection signal lines coupled to at least one of the first signal lines or the second signal lines. At least one of the inspection signal lines is discontinuous at a region overlapping the power source supply line and ends of the discontinuous inspection signal line at the region overlapping the power source supply line are coupled to each other through a conductive region under the inspection signal line.02-05-2009

Patent applications by Keun-Soo Lee, Suwon-Si KR

Keun-Soo Lee, Yongin-City KR

Patent application numberDescriptionPublished
20100026173METHOD OF DEPOSITING LIGHT EMITTING LAYER OF ORGANIC EL DEVICE, METHOD OF MANUFACTURING ORGANIC EL DEVICE, AND ORGANIC EL DEVICE MANUFACTURED BY THE METHOD - A method of depositing a light emitting layer of an organic EL device in which a subpixel combination having a plurality of different colors is set as a unit pixel, a plurality of subpixels are sequentially and alternately arranged in a row direction, and a plurality of subpixels of the same color are arranged in a column direction, includes first depositing the light emitting layer using a mask having a plurality of opening portions corresponding to positions of the subpixels of the same color arranged in any of an odd numbered row and an even-numbered column of the subpixels, and second depositing the light emitting layer by moving the mask to prevent the light emitting layer from being deposited at a subpixel adjacent to the subpixel where the light emitting layer is deposited during the first deposition operation, using the same opening portion of the mask used for the first deposition operation of the light emitting layer.02-04-2010
20100193779BOTTOM GATE THIN FILM TRANSISTOR, FLAT PANEL DISPLAY HAVING THE SAME AND METHOD OF FABRICATING THE SAME - A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.08-05-2010
20100310974Method of fabricating photo mask for organic light emitting display and photo mask so fabricated - A method of fabricating a photo mask for an organic light emitting display comprises forming a light shielding layer on a transparent substrate, coating the light shielding layer with an electron beam resist, performing exposure on the electron beam resist by a vector scan method in accordance with a specific pattern and using an electron beam having a predetermined accelerating voltage, developing the exposed electron beam resist to form an electron beam resist pattern having the specific pattern, and etching the light shielding layer using the electron beam resister pattern as an etching mask. The specific pattern has a shape corresponding to transistors included in a pixel of an organic light emitting display and elements that constitute a capacitor.12-09-2010
20110024756ORGANIC LIGHT EMITTING DISPLAY - The general inventive concept relates to an organic light emitting display that has the same area where the upper and lower electrodes of a capacitor are overlapped for adjacent pixels, for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different. This thereby prevents the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded.02-03-2011
20110248953Touch screen panel - A touch screen panel includes a transparent substrate, connecting patterns on the transparent substrate, the connecting patterns including a plurality of first connecting patterns arranged in a first direction and a plurality of second connecting patterns arranged in a second direction, sensing cells including a plurality of first sensing cells connected in the first direction by the first connecting patterns and a plurality of second sensing cells connected in the second direction by the second connecting patterns, and conductive dummy patterns between adjacent sensing cells, the conductive dummy patterns and sensing cells being positioned at different height levels relative to the transparent substrate, and the conductive dummy patterns including prominences projected toward the sensing cells and partially overlapping the sensing cells.10-13-2011
20120062487Touch Screen Panel and Display Device Having the Same - A touch screen panel and a display device having the same are capable of improving visibility and suppressing the occurrence of a failure caused by static electricity. In one embodiment, the touch screen panel includes a plurality of first sensing cells arranged along a first direction for each column on a transparent substrate. A first connection pattern electrically connects adjacent first sensing cells to each other. A plurality of second sensing cells are arranged along a second direction for each row while being spaced apart from the first sensing cells. A second connection pattern electrically connects adjacent second sensing cells to each other. In the touch screen panel, the first connection pattern comprises a pair of metal patterns and two pairs of dummy transparent patterns.03-15-2012
20120075257Touch Screen Panel - A touch screen panel includes a transparent substrate. A plurality of first and second sensing cells are formed so as to be connected along first and second directions, respectively. The second sensing cells are disposed between the first sensing cells. A plurality of first and second connection patterns connect the first and second sensing cells to one another along the first and second directions, respectively. A first insulating layer is interposed between the first second connection patterns. In the touch screen panel, each of the first connection patterns includes a main bridge pattern separately patterned in a different layer from the first sensing cells connected by the main bridge pattern to connect adjacent first sensing cells to other along the first direction, and one or more sub-bridge patterns which branch from the main bridge pattern, and which have both ends connected to the main bridge pattern so as to form a detour path.03-29-2012

Patent applications by Keun-Soo Lee, Yongin-City KR

Keun-Soo Song, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20090134926MULTI-PHASE NEGATIVE DELAY PULSE GENERATOR - A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have a first negative delay property respectively and of which an even number is ring-coupled; and a second delay block including second unit blocks which have a second negative delay property respectively and of which even number is ring-coupled. The number of the first unit block and the number of the second unit block are the same. A plurality of output nodes is formed based on one-to-one sharing between the first unit block and the second unit block having output signals of different level. Each output node outputs a pulse generated by racing the output signals of different level to each other which are provided from the first unit block and the second unit block connected to the each output node.05-28-2009
20100290302FUSE CIRCUIT AND DRIVING METHOD THEREOF - A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.11-18-2010