Kessenich
Grace R. Kessenich, Somerville, MA US
Patent application number | Description | Published |
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20080202664 | Method of manufacturing a piezoelectric package having a composite structure - A piezoelectric package comprises a piezoelectric plate having a first planar surface and a second planar surface that are electrically isolated from each other. The piezoelectric package further comprises a first electrically conductive layer electrically coupled to the first planar surface, and a second electrically conductive layer electrically coupled to the second planar surface. The piezoelectric package further comprises a first electrically insulative material (e.g., a rigid fiber composite material) encapsulating the piezoelectric plate and at least portions of the first and second electrically conductive layers. | 08-28-2008 |
20080203851 | PIEZOELECTRIC PACKAGE WITH POROUS CONDUCTIVE LAYERS - A piezoelectric package comprises a piezoelectric plate having a first planar surface and a second planar surface that are electrically isolated from each other. The piezoelectric package further comprises a first electrically conductive layer electrically coupled to the first planar surface, and a second electrically conductive layer electrically coupled to the second planar surface. The piezoelectric package further comprises a first electrically insulative material (e.g., a rigid fiber composite material) encapsulating the piezoelectric plate and at least portions of the first and second electrically conductive layers. | 08-28-2008 |
20080218026 | Piezoelectric package with enlarged conductive layers - A piezoelectric package comprises a piezoelectric plate having a first planar surface and a second planar surface that are electrically isolated from each other. The piezoelectric package further comprises a first electrically conductive layer electrically coupled to the first planar surface, and a second electrically conductive layer electrically coupled to the second planar surface. The piezoelectric package further comprises a first electrically insulative material (e.g., a rigid fiber composite material) encapsulating the piezoelectric plate and at least portions of the first and second electrically conductive layers. | 09-11-2008 |
20100013352 | UNIMORPH/BIMORPH PIEZOELECTRIC PACKAGE - A piezoelectric package comprises an upper and lower piezoelectric plates, each having opposing electrodes. The piezoelectric package further comprises an electrically insulative structure encapsulating the piezoelectric plates. The piezoelectric package further comprises first and second external connectors mounted to the insulative structure. The connectors respectively have connector terminals that are electrically coupled to the electrodes in different orders, and have geometric arrangements that are identical, such that a single interface device can be selectively mated to either of the connectors. The piezoelectric package may be incorporated into a system that comprises electronic circuitry configured for operating the piezoelectric package, and a single interface device electrically coupled between the electronic circuitry and either of the external connectors of the piezoelectric package to selectively configure the package between a unimorph and a bimorph. | 01-21-2010 |
Jeffrey Kessenich, Boise, ID US
Patent application number | Description | Published |
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20090003078 | Program-verify method - Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations. | 01-01-2009 |
20100046303 | PROGRAM-VERIFY METHOD - Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations. | 02-25-2010 |
Jeffrey A. Kessenich, Vancouver, WA US
Patent application number | Description | Published |
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20150364213 | PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS - Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current. | 12-17-2015 |
Jeffrey Alan Kessenich, Boise, ID US
Patent application number | Description | Published |
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20100284219 | MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE - Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold. | 11-11-2010 |
20120269004 | MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE - A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold. | 10-25-2012 |