# Kerim Kalafala, Rhinebeck US

## Kerim Kalafala, Rhinebeck, NY US

Patent application number | Description | Published |
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20080209372 | Estimation Of Process Variation Impact Of Slack In Multi-Corner Path-Based Static Timing Analysis - A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. | 08-28-2008 |

20080209373 | METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS - Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability. | 08-28-2008 |

20080209374 | Parameter Ordering For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion. | 08-28-2008 |

20080209375 | Variable Threshold System and Method For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. | 08-28-2008 |

20090210839 | TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER - A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin. | 08-20-2009 |

20090276743 | SYSTEM AND METHOD FOR COMPUTING PROXY SLACK DURING STATISTIC ANALYSIS OF DIGITAL INTEGRATED CIRCUITS - A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value. | 11-05-2009 |

20100180242 | Method and system for efficient validation of clock skews during hierarchical static timing analysis - A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis. | 07-15-2010 |

20100180244 | Method For Efficiently Checkpointing And Restarting Static Timing Analysis Of An Integrated Circuit Chip - A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced. | 07-15-2010 |

20100211922 | Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits - A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction. | 08-19-2010 |

20120047477 | Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis - Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof. | 02-23-2012 |

20120124534 | System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times - A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack. | 05-17-2012 |

20120185810 | Method for Improving Static Timing Analysis and Optimizing Circuits Using Reverse Merge - Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs. | 07-19-2012 |

20120311514 | Decentralized Dynamically Scheduled Parallel Static Timing Analysis - A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes. | 12-06-2012 |

20120311515 | Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs - A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together. | 12-06-2012 |