| Patent application number | Description | Published |
|---|
| 20100127937 | Antenna Integrated in a Semiconductor Chip - An antenna structure is integrated in a semiconductor chip. The antenna structure is formed by at least one of: a) one or more through-silicon vias (TSVs), and b) one or more crack stop structures. In certain embodiments, the antenna structure includes an antenna element formed by the TSVs. The antenna structure may further include a directional element formed by the crack stop structure. In certain other embodiments, the antenna structure includes an antenna element formed by the crack stop structure, and the antenna structure may further include a directional element formed by the TSVs. | 05-27-2010 |
| 20100148371 | Via First Plus Via Last Technique for IC Interconnects - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 06-17-2010 |
| 20100155931 | Embedded Through Silicon Stack 3-D Die In A Package Substrate - An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack. | 06-24-2010 |
| 20100174661 | Wireless Branding - A device wirelessly broadcasts branding information associated with a consumer product attached to the device. The branding information is sent to a receiver located remotely from the product. | 07-08-2010 |
| 20100261310 | Via First Plus Via Last Technique for IC Interconnect - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 10-14-2010 |
| 20110042829 | IC Interconnect - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 02-24-2011 |
| Patent application number | Description | Published |
|---|
| 20090273068 | 3-D Integrated Circuit Lateral Heat Dissipation - By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations. | 11-05-2009 |
| 20090322366 | Integrated Tester Chip Using Die Packaging Technologies - By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardizes across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized. | 12-31-2009 |
| 20090322368 | Integrated Tester Chip Using Die Packaging Technologies - By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized. | 12-31-2009 |
| 20100059869 | Systems and Methods for Enabling ESD Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 03-11-2010 |
| 20100191072 | Button Sensor - A hermetically sealed electronic closure device, or button, includes a self-renewing power source, a sensor for measuring a metric, a memory storing information, a data processing circuit for controlling operations of the device, and a transceiver for sending and receiving information. The device is a standard part of a clothing item that is inconspicuous to a wearer of the clothing item. | 07-29-2010 |
