Patent application number | Description | Published |
20090003070 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string. | 01-01-2009 |
20100001401 | SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT LAYER MADE OF COPPER - A semiconductor device includes an interlayer insulating film, a barrier metal layer, a conductive layer and a first insulating film. The barrier metal layer is formed on a bottom surface and a side face of a trench made in the interlayer insulating film. The conductive layer is formed on the barrier metal layer. The conductive layer has its upper surface lower than an upper surface of an opening of the trench and buries a part of the trench. The first insulating film is formed on the conductive layer and is formed on the barrier metal layer on a side face of the opening of the trench. The first insulating film is made of a material having a dielectric constant higher than that of the interlayer insulating film. | 01-07-2010 |
20100270527 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE PHASE-CHANGE MEMORY DEVICE - A phase-change memory device has a plurality of first wiring lines; a plurality of memory cells that are provided on the plurality of first wiring lines; a plurality of second wiring lines that are provided on the plurality of memory cells, respectively; and an interlayer insulating film that is formed between the plurality of first wiring lines and the plurality of second wiring lines and insulates the plurality of first wiring lines from the plurality of second wiring lines; wherein each of the memory cells includes a heat source element that is supplied with a current and generates heat and a phase-change element that is changed to an amorphous state or a crystalline state according to a cooling speed after being heated by the heat source element, a resistance value of the phase-change element varying with the change in the state, and wherein a void is formed between the two adjacent memory cells in the interlayer insulating film. | 10-28-2010 |
20110069553 | SEMICONDUCTOR STORAGE DEVICE COMPRISING DOT-TYPE CHARGE ACCUMULATION PORTION AND CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first insulation film, Charge accumulation portions, a second insulation film, and a control gate. The first insulation film is located on an active area (AA). The charge accumulation portions comprise minute crystals arranged on the first insulation film. A density of the charge accumulation portions at an end portion in an AA width direction of the first insulation film is higher than a density of the charge accumulation portions at a central potion in the AA width direction. The second insulation film is located on the first insulation film so as to coat the charge accumulation portions. The control gate is located on the second insulation film. | 03-24-2011 |
20110157997 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF READING DATA THEREFROM, AND SEMICONDUCTOR DEVICE - A control circuit is configured to performs, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution that is the maximum distribution of the threshold voltage distributions. The circuit is configured to apply, at least during a verify operation in a first write operation conducted before a second write operation that completes writing to the first threshold voltage distribution, a second read-pass voltage lower than the first read-pass voltage to the unselected memory cell, and apply to the semiconductor layer and the source-line a positive voltage. | 06-30-2011 |
20110233622 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction. | 09-29-2011 |
20120198297 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit. | 08-02-2012 |
20130043523 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of gate electrode structures formed on a semiconductor substrate and an insulating film which covers the gate electrode structures and has an air gap in it. Each of the gate electrode structures includes a gate insulting film, a charge storage layer, an intermediary insulating film, and a control gate electrode. The control gate electrode includes a first control gate and a second control gate whose width is greater than that of the first control gate. The air gap is formed so as to be higher than a space between the control gate electrodes and than the control gate electrodes. | 02-21-2013 |
20130187208 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction. | 07-25-2013 |
20150049551 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter. | 02-19-2015 |