Patent application number | Description | Published |
20100176488 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region. | 07-15-2010 |
20100237400 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a multilayer body with a plurality of insulating films and electrode films alternately stacked therein; a plurality of select gate electrodes provided on the multilayer body, extending in one direction orthogonal to a stacking direction of the multilayer body, and spaced from each other; semiconductor pillars penetrating through the multilayer body and the select gate electrodes; and a charge storage film provided between one of the electrode films and one of the semiconductor pillars, two neighboring ones of the semiconductor pillars penetrating through a common one of the select gate electrodes and penetrating through mutually different positions in a width direction of the select gate electrodes. | 09-23-2010 |
20120012805 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first interconnect, a nanomaterial aggregate layer, and a second interconnect. The nanomaterial aggregate layer is provided on the first interconnect. The nanomaterial aggregate layer includes an aggregation of a plurality of micro conductive bodies. The second interconnect is provided on the nanomaterial aggregate layer. At least a lower portion of the nanomaterial aggregate layer is disposed inside the second interconnect as viewed from above. | 01-19-2012 |
20120025159 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes. | 02-02-2012 |
20120056145 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 03-08-2012 |
20120064693 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region. | 03-15-2012 |
20120097914 | MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction. | 04-26-2012 |
20120104352 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer. | 05-03-2012 |
20120205609 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer. | 08-16-2012 |
20130295743 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 11-07-2013 |
20140147942 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer. | 05-29-2014 |