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Ken Matsubara
Ken Matsubara, Osaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20080197743 | Electric Motor and Electric Power Steering Apparatus - An electric motor ( | 08-21-2008 |
| 20100314192 | VEHICLE STEERING APPARATUS AND MANUFACTURING METHOD OF SAME - An electric power steering apparatus ( | 12-16-2010 |
| 20110000737 | VEHICLE STEERING APPARATUS - Disclosed is a vehicle steering apparatus ( | 01-06-2011 |
Ken Matsubara, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100232232 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array. | 09-16-2010 |
| 20100290290 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal. | 11-18-2010 |
Ken Matsubara, Higashimurayama JP
| Patent application number | Description | Published |
|---|---|---|
| 20080225602 | DATA PROCESSING SYSTEM AND NONVOLATILE MEMORY - Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough. | 09-18-2008 |
| 20090273014 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate. | 11-05-2009 |
Ken Matsubara, Matsubara-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080277189 | ELECTRIC POWER STEERING APPARATUS - It is an object of the present invention to provide an electric power steering apparatus to be small and compact. | 11-13-2008 |
| 20090079373 | MOTOR CONTROLLER AND ELECTRIC POWER STEERING SYSTEM - A current sensor of a motor controller detects the current applied to a motor drive circuit and thus a phase where a failure cannot be detected would occur without taking any measures. However, an abnormal current monitor section contained in a microcomputer receives a voltage signal of an average value of the currents detected in the current sensor by allowing a signal to pass through a first LPF having a cutoff frequency sufficiently lower than the frequency of a PWM signal. Therefore, whether or not the value is within a predetermined normal range is checked, whereby whether or not some failure containing a failure of the current sensor occurs can be easily determined about every phase. | 03-26-2009 |
Ken Matsubara, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20120002498 | NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM - Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized. | 01-05-2012 |