Patent application number | Description | Published |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |
20140339651 | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness. | 11-20-2014 |
20140339669 | Semiconductor Device with a Field Plate Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric. | 11-20-2014 |
20140339670 | Semiconductor Device with a Thick Bottom Field Plate Trench Having a Single Dielectric and Angled Sidewalls - Disclosed is a power device, such as a power MOSFET device and a method for fabricating same. The device includes a field plate trench. The field plate trench has a predetermined width and a predetermined sidewall angle. The device further includes a single trench dielectric on sidewalls of the field plate trench and at a bottom of the field plate trench. The single trench dielectric has a bottom thickness that is greater than a sidewall thickness. The device also includes a field plate situated within the single trench dielectric. | 11-20-2014 |
20140374825 | Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches - Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another. | 12-25-2014 |
20150325685 | Power Semiconductor Device with Low RDSON and High Breakdown Voltage - A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench. | 11-12-2015 |
20160104766 | Power Semiconductor Device with Source Trench and Termination Trench Implants - A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench. | 04-14-2016 |
20160104773 | Semiconductor Structure Having Integrated Snubber Resistance and Related Method - A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions. | 04-14-2016 |
Patent application number | Description | Published |
20100258710 | OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS - An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device. A third opaque light barrier portion, extending from the first light barrier portion in a direction towards to the light detector, is configured to reduce an amount of specular reflections that would be detected by the light detector, if a light transmissive cover plate were placed over the optical sensor device. | 10-14-2010 |
20100258712 | OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS - An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source. | 10-14-2010 |
20100259766 | OPTICAL SENSORS AND METHODS FOR PROVIDING OPTICAL SENSORS - Provided herein are optical sensor devices, methods for making the same, and systems including the same. An optical sensor device, according to an embodiment, includes a light detector die and a light source die attached to the same or different die attachment substrates so that there is a space between the light source die and the light detector die. A light transmissive material covers the light detector die, the light source die and at least a portion of the space between the light detector die and the light source die. A groove is formed (e.g., saw, blade or laser cut, or cast) in the light transmissive material between the light detector die and the light source die, and an opaque material is put within the groove to provide a light barrier between the light detector die and the light source die. | 10-14-2010 |
20100276701 | LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTURE AND METHOD - A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design. | 11-04-2010 |
20110033724 | Tie-Bar Configuration For Leadframe Type Carrier Strips - A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context. | 02-10-2011 |
20110163434 | STACKED POWER CONVERTER STRUCTURE AND METHOD - A power converter can include an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The power converter can further include a controller integrated circuit (IC) formed on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. The PowerDie can be attached to a die pad of a leadframe, and the controller IC die can be attached to an active surface of the first die such that the first die is interposed between the controller IC die and the die pad. | 07-07-2011 |
20120098090 | HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS - A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die. | 04-26-2012 |
20130314879 | CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY (HDA) POWER MODULE, AND METHOD OF MAKING SAME - A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components. | 11-28-2013 |
Patent application number | Description | Published |
20110134613 | STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANUFACTURING SAME - An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor. | 06-09-2011 |
20120063038 | POWER-SUPPLY MODULE WITH ELECTROMAGNETIC-INTERFERENCE (EMI) SHIELDING, COOLING, OR BOTH SHIELDING AND COOLING, ALONG TWO OR MORE SIDES - An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components. | 03-15-2012 |
20120290255 | CLEAR LAYER ISOLATION - A method for optical isolation in a clear mold package is provided. The method comprises forming a substrate and mounting a first component on the substrate. The method also comprises depositing a clear layer over the first component and the substrate and fabricating a trench in the clear layer near the first component, wherein the trench extends from a top surface of the substrate to the top surface of the clear layer. Further, the method comprises depositing an opaque material within the trench. | 11-15-2012 |
20130015592 | BOND PAD CONFIGURATIONS FOR SEMICONDUCTOR DIES - A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads. | 01-17-2013 |
20130181332 | PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY - Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe. | 07-18-2013 |
20130187260 | PACKAGED SEMICONDUCTOR DEVICES, AND RELATED METHODS AND SYSTEMS - A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers. | 07-25-2013 |
20130270701 | SYSTEM AND METHODS FOR WIRE BONDING - A semiconductor package comprises a bond pad formed on a first semiconductor die, a surface of the bond pad exposed through an opening in a passivation layer on the first semiconductor die; a raised conductive area formed on top of a passivation layer on a second semiconductor die; and a bond wire having a first end coupled to the bond pad via a ball bond and a second end coupled directly to a surface of the raised conductive area via a stitch bond. The raised conductive area is comprised of a plurality of metal layers, each of the metal layers comprised of a respective material and having a respective thickness. The thickness and material of at least one of the plurality of metal layers is selected such that a hardness of the raised conductive area is at least as hard as a hardness of the bond wire. | 10-17-2013 |
20130313694 | PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE - Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate. | 11-28-2013 |
20150194370 | PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE - Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate. | 07-09-2015 |
Patent application number | Description | Published |
20130007865 | System and Method for Tracking Network Traffic of users in a Research Panel - A system, computer-readable storage medium storing at least one program, and a computer-implemented method for tracking network traffic of users in a research panel are presented. A packet for a network device coupled to the network access device is received. An indicia corresponding to a presumptive user of the network device is obtained, where the presumptive user includes a member of a set of known users. One or more logging rules is applied to the network device, where the one or more applied logging rules correspond to the obtained indicia. Information relating to the packet is stored when the packet satisfies at least one of the logging rules applied to the network device. | 01-03-2013 |
20140259139 | System and Method for Tracking Network Traffic of Users in a Research Panel - A network access device directs an electronic device, distinct from the network access device, to display graphical user interface, the graphical user interface comprising a network access self-identification user interface. The network access device obtains a selection of a user identification option, through the self-identification user interface. In accordance with a determination that the selected user identification option corresponds to a registered user (e.g., a registered user in a research panel), of a previously defined set of registered users of the network access device, the network access device enables access to a communications network, in accordance with the application of one or more logging rules corresponding to the selected user. Further, in accordance with a determination that the selected user identification option corresponds to an unregistered, guest user, the network access device enables access to the communications network, without the application of any logging rules. | 09-11-2014 |
Patent application number | Description | Published |
20090308732 | APPARATUS AND METHOD FOR UNIFORM DEPOSITION - Embodiments of the present invention generally relate to an apparatus and method for uniform sputter depositing of materials into the bottom and sidewalls of high aspect ratio features on a substrate. In one embodiment, a sputter deposition system includes a collimator that has apertures having aspect ratios that decrease from a central region of the collimator to a peripheral region of the collimator. In one embodiment, the collimator is coupled to a grounded shield via a bracket member that includes a combination of internally and externally threaded fasteners. In another embodiment, the collimator is integrally attached to a grounded shield. In one embodiment, a method of sputter depositing material includes pulsing the bias on the substrate support between high and low values. | 12-17-2009 |
20120231633 | OFF-ANGLED HEATING OF THE UNDERSIDE OF A SUBSTRATE USING A LAMP ASSEMBLY - Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed. | 09-13-2012 |
20130196514 | OFF-ANGLED HEATING OF THE UNDERSIDE OF A SUBSTRATE USING A LAMP ASSEMBLY - Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed. | 08-01-2013 |
20130270107 | OFF-ANGLED HEATING OF THE UNDERSIDE OF A SUBSTRATE USING A LAMP ASSEMBLY - Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed. | 10-17-2013 |
20140216585 | GAS INJECTION APPARATUS AND SUBSTRATE PROCESS CHAMBER INCORPORATING SAME - Methods and apparatus for mixing and delivery of process gases are provided herein. In some embodiments, a gas injection apparatus includes an elongate top plenum comprising a first gas inlet; an elongate bottom plenum disposed beneath and supporting the top plenum, the bottom plenum comprising a second gas inlet; a plurality of first conduits disposed through the bottom plenum and having first ends fluidly coupled to the top plenum and second ends disposed beneath the bottom plenum; and a plurality of second conduits having first ends fluidly coupled to the bottom plenum and second ends disposed beneath the bottom plenum; wherein a lower end of the bottom plenum is adapted to fluidly couple the gas injection apparatus to a mixing chamber such that the second ends of the plurality of first conduits and the second ends of the plurality of second conduits are in fluid communication with the mixing chamber. | 08-07-2014 |
20150329966 | SHOWERHEAD DESIGN - Embodiments described herein relate to a showerhead having a reflector plate with a gas injection insert for radially distributing gas. In one embodiment, a showerhead assembly includes a reflector plate and a gas injection insert. The reflector plate includes at least one gas injection port. The gas injection insert is disposed in the reflector plate, and includes a plurality of apertures. The gas injection insert also includes a baffle plate disposed in the gas injection insert, wherein the baffle plate also includes a plurality of apertures. A first plenum is formed between a first portion of the baffle plate and the reflector plate, and a second plenum is formed between a second portion of the baffle plate and the reflector plate. The plurality of apertures of the gas injection insert and the plurality of apertures of the baffle plate are not axially aligned. | 11-19-2015 |
20150345019 | METHOD AND APPARATUS FOR IMPROVING GAS FLOW IN A SUBSTRATE PROCESSING CHAMBER - Embodiments of methods and apparatus for improving gas flow in a substrate processing chamber are provided herein. In some embodiments, a substrate processing chamber includes: a chamber body and a chamber lid defining an interior volume; a substrate support disposed within the interior volume and having a support surface to support a substrate; a gas passageway disposed in the lid opposite the substrate support to supply a gas mixture to the interior volume, the gas passageway including a first portion and a second portion; a first gas inlet disposed in the first portion to supply a first gas to the first portion of the gas passageway; and a second gas inlet disposed in the second portion to supply a second gas to the second portion. | 12-03-2015 |
20150371827 | BIAS VOLTAGE FREQUENCY CONTROLLED ANGULAR ION DISTRIBUTION IN PLASMA PROCESSING - The angular ion distribution in plasma processing is controlled using a bias voltage frequency. In one example, a plasma containing gas ions is generated in a plasma chamber. The plasma sheath is modified using an aperture disposed between the plasma sheath and the workpiece so that the plasma sheath takes a shape above the aperture. An oscillating radio frequency bias voltage is generated and applied to a workpiece holder. The workpiece holder applies the bias voltage to the workpiece to generate a workpiece bias voltage with respect to the plasma to attract ions across the plasma sheath toward the workpiece. The aperture and the frequency of the bias voltage control an angle at which the ions are attracted toward the workpiece. | 12-24-2015 |