Patent application number | Description | Published |
20110092072 | HEATING PLATE WITH PLANAR HEATING ZONES FOR SEMICONDUCTOR PROCESSING - A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic or polymer sheets having planar heater zones, power supply lines, power return lines and vias. | 04-21-2011 |
20130072025 | COMPONENT OF A SUBSTRATE SUPPORT ASSEMBLY PRODUCING LOCALIZED MAGNETIC FIELDS - A component of a substrate support assembly such as a substrate support or edge ring includes a plurality of current loops incorporated in the substrate support and/or the edge ring. The current loops are laterally spaced apart and extend less than halfway around the substrate support or edge ring with each of the current loops being operable to induce a localized DC magnetic field of field strength less than 20 Gauss above a substrate supported on the substrate support during plasma processing of the substrate. When supplied with DC power, the current loops generate localized DC magnetic fields over the semiconductor substrate so as to locally affect the plasma and compensate for non-uniformity in plasma processing across the substrate. | 03-21-2013 |
20140045337 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - An exemplary method is directed to powering heaters in a substrate support assembly on which a semiconductor substrate is supported. The support assembly has an array of heaters powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to a power supply and at least two of the heaters and each power return line is connected to at least two of the heaters, and a switching device which independently connects each one of the heaters to one of the power supply lines and one of the power return lines so as to provide time-averaged power to each of the heaters by time divisional multiplexing of switches of the switching device. The method includes supplying power to each of the heaters sequentially using a time-domain multiplexing scheme. | 02-13-2014 |
20140047705 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - An exemplary method for manufacturing a heating plate for a substrate support assembly includes forming holes in at least one sheet, printing a slurry of conductor powder, or pressing a precut metal foil, or spraying a slurry of conductor powder, on the at least one sheet to form the planar heater zones, the power supply lines, and power return lines. The holes in the at least one sheet are filled with a slurry of conductor powder to form power supply and power return vias. The sheets are then aligned, pressed, and bonded to form the heating plate. | 02-20-2014 |
20140096909 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - A heating plate of a semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a first layer with an array of heater zones operable to tune a spatial temperature profile on the semiconductor substrate, and a second layer with one or more primary heaters to provide mean temperature control of the semiconductor substrate. The heating plate can be incorporated in a substrate support wherein a switching device independently supplies power to each one of the heater zones to provide time-averaged power to each of the heater zones by time divisional multiplexing of the switches. | 04-10-2014 |
20140220709 | CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS - Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile. | 08-07-2014 |
20150053347 | CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS - Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile. | 02-26-2015 |
20150179412 | EDGE RING DIMENSIONED TO EXTEND LIFETIME OF ELASTOMER SEAL IN A PLASMA PROCESSING CHAMBER - An edge ring configured to surround an outer periphery of a substrate support in a plasma processing chamber wherein plasma is generated and used to process a substrate is disclosed, the substrate support comprising a base plate, a top plate, an elastomer seal assembly between the base plate and the top plate, and an elastomer seal configured to surround the elastomer seal assembly. The edge ring includes an upper inner surface having an edge step directed towards an interior portion of the edge ring and arranged to extend from an outer periphery of a top surface of the top plate to an outer periphery of an upper surface of the base plate, a lower inner surface, an outer surface, a lower surface extending from the lower inner surface to the outer surface, and a top surface extending from the outer surface to the upper inner surface. | 06-25-2015 |
20150181683 | ELECTROSTATIC CHUCK INCLUDING DECLAMPING ELECTRODE AND METHOD OF DECLAMPING - A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode. | 06-25-2015 |