Patent application number | Description | Published |
20100169556 | NONVOLATILE STORAGE DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION RECORDING METHOD - A nonvolatile storage device includes a nonvolatile memory configured to store user data and management information used to manage the user data on a file system, and a medium controller configured to determine whether a command input from a host device is used for the user data or the management information, the command describing content of processing performed for the user data or the management information, and switch between control methods used for the nonvolatile memory on the basis of the determination result. | 07-01-2010 |
20100287332 | DATA STORING SYSTEM, DATA STORING METHOD, EXECUTING DEVICE, CONTROL METHOD THEREOF, CONTROL DEVICE, AND CONTROL METHOD THEREOF - A data storing system including: a non-volatile memory configured to have a plurality of memory blocks each capable of independently operating and allow random access to each of addresses; a controller configured to control writing of data to the non-volatile memory; and an executing unit configured to execute a predetermined application, wherein the executing unit decides the number of interleaves indicating the number of memory blocks operated in parallel among the plurality of memory blocks, and the executing unit notifies the controller of the decided number of interleaves. | 11-11-2010 |
20110010580 | Memory apparatus, memory controlling method and program - A memory apparatus includes a memory having a main memory area and a replacement area, and a memory controller having a function of issuing instructions corresponding to commands to carry out transmission and reception of data and reading of status information of the memory. | 01-13-2011 |
20110035646 | NONVOLATILE RANDOM ACCESS MEMORY AND NONVOLATILE MEMORY SYSTEM - A nonvolatile random access memory includes: a nonvolatile storage area that is randomly accessible and includes a data area to store data and an error-correcting-code area to store an error correcting code, the data area including at least one data area to which a data area unit size is assigned, the error-correcting-code area including at least one error-correcting-code area to which an error-correcting-code-area unit size is assigned; and a nonvolatile storage area controller to set a data size used when the at least one data area is accessed, as the data area unit size. The nonvolatile storage area controller manages the data area and the error-correcting-code area based on the set data area unit size and assigns the at least one error-correcting-code area with the error-correcting-code-area unit size to the at least one data area with the data area unit size based on the data area unit size. | 02-10-2011 |
20110066923 | NONVOLATILE MEMORY APPARATUS, MEMORY CONTROLLER, AND MEMORY SYSTEM - Disclosed herein is a nonvolatile memory apparatus including, a nonvolatile memory section, a standard error correction code processing section, an extended error correction code processing section, and a control section. | 03-17-2011 |
20110087836 | STORAGE UNIT AND MEMORY SYSTEM - A storage unit includes: a random access memory device and a storage device to be accessed using an address in units of word and sector, respectively; and a storage controller controlling accesses to the random access memory device and the storage device according to the addresses designated via a bus. The storage controller includes first and second interface functions for access to data stored on the storage device and the random access memory designated using the sector address and the word address provided via the bus, respectively, a function of using the random access memory device as a first disk cache and determining data to be saved in the random access memory device in response to the access by the first interface function, and functions of transferring the data designated using the sector address by repeating register access and by a bus master function as continuous word-sized data through the bus. | 04-14-2011 |
20110119558 | NONVOLATILE MEMORY AND MEMORY SYSTEM - Disclosed herein is a nonvolatile memory, including: a memory area including a data area configured to retain data and an error correction code area configured to retain an error correction code known as ECC; and a control unit configured to control access to the memory area. The control unit includes an error detection and correction function configured to detect an error in the data read from the data area and to correct the detected error, at least one save area configured such that if data at a designated address and ECC corresponding thereto are read from the memory area and if an error is detected, then the save area retaining the address and correct data corresponding thereto, and a validity presentation block configured to indicate whether or not the address and the correct data retained in the save area are valid. | 05-19-2011 |
Patent application number | Description | Published |
20090061688 | Card-type peripheral device - A card-type peripheral device includes an electronic component disposed in a case, and a terminal part including connection terminals connectable with a to-be-connected device, wherein a function of the electronic component and the number of terminals of the terminal part are maintained to be compatible with those of the to-be-connected device, and the outside dimensions of the case are set to be smaller than the outside dimensions of the to-be-connected device and greater than the outside dimensions of a predetermined small-size card. | 03-05-2009 |
20090063743 | Card-type peripheral device - A card-type peripheral device includes an electronic component including a memory disposed in a case, a terminal part including connection terminals connectable with a to-be-connected device, and a switch for disabling writing to the memory. The card-type peripheral device further includes a signal terminal capable of transmitting a signal indicating the status of the switch to the to-be-connected device. | 03-05-2009 |
20090077295 | Card-type peripheral device - A card-type peripheral device having a plurality of specifications of external interfaces includes a connector configured to connect the card-type peripheral device to a connectable device connectable to the card-type peripheral device, the connector including a dedicated terminal in which an interface to be used is set; an electronic component configured to be accessed via the set interface; a plurality of interface function units each configured to control an interface compliant with one of the plurality of specifications; and a communication function unit configured to perform communication with the electronic component using one of the interface function units having a specification corresponding to a setting of the dedicated terminal. | 03-19-2009 |
20120311408 | NONVOLATILE MEMORY, MEMORY CONTROLLER, NONVOLATILE MEMORY ACCESSING METHOD, AND PROGRAM - Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode. | 12-06-2012 |
20130104001 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block. | 04-25-2013 |
20130117632 | STORAGE CONTROL APPARATUS - Embodiments of the technology disclosed herein are intended to flexibly set the rules of attaching error correction codes to a group of data sequences stored in a memory. A storage control apparatus has an error correction code attachment rule hold block and an error correction portion. The error correction code attachment rule hold block holds the rules of attaching error correction codes to a group of data sequences stored in a memory by relating the rules with the data for each address of the group of data sequences. If an access occurs to the memory, the error correction portion executes error correction processing on a group of data sequences stored in the memory in accordance with the attachment rules related to the address at which the access occurred. | 05-09-2013 |
20130139030 | STORAGE CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROLLING METHOD - A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code. | 05-30-2013 |
20130179646 | STORAGE CONTROL DEVICE, STORAGE DEVICE, AND CONTROL METHOD FOR CONTROLLING STORAGE CONTROL DEVICE - A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read. | 07-11-2013 |
20130254498 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD THEREFOR - A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed. | 09-26-2013 |
20130262737 | STORAGE CONTROL APPARATUS , STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address. | 10-03-2013 |
20130272078 | STORAGE CONTROLLING APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROLLING METHOD - Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data. | 10-17-2013 |
20130275818 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory. | 10-17-2013 |
20130282993 | STORAGE CONTROL DEVICE, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite. | 10-24-2013 |
20130290620 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS AND PROCESSING METHOD - A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line. | 10-31-2013 |
20130339637 | MEMORY CONTROL APPARATUS, MEMORY APPARATUS, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD FOR USE THEREWITH - There is provided a memory control apparatus including: a pre-read processing section reading pre-read data from a data area to be written to before a write process in a predetermined data area of a memory cell array; a conversion determination section which, upon selectively allowing the pre-read data to transition to either a first conversion candidate or a second conversion candidate of the write data to be written in the write process, generates a determination result for selecting either of the candidates based on the larger of two values of which one is the number of bits transitioning from the first value to the second value and of which the other is the number of bits transitioning from the second value to the first value; and a conversion control section selecting either of the candidates in accordance with the determination result. | 12-19-2013 |
20140009996 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF - There is provided a storage control device including a read processing unit that reads data and inversion state information indicating whether the data is in an inverted state or a non-inverted state from a specific region of a memory cell array that stores the data and the inversion state information with first intensity in association, and a write processing unit that writes data obtained by inverting the data and a state obtained by changing a state indicated by the inversion state information to an opposite state in the specific region with second intensity that is different from the first intensity. | 01-09-2014 |
20140025907 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, AND PROCESSING METHODS THEREOF - There is provided a storage control apparatus including a memory state acquisition unit acquiring a storage state of a memory associated with a write target, and an operation instruction generation unit generating an operation instruction of at least 2 bits per cell of the memory associated with the write target, from the acquired storage state and write data. | 01-23-2014 |
20140059268 | MEMORY CONTROL DEVICE, NON-VOLATILE MEMORY, AND MEMORY CONTROL METHOD - Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written. | 02-27-2014 |
20140059404 | MEMORY CONTROL DEVICE, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD - There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request. | 02-27-2014 |
20140122972 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address. | 05-01-2014 |
20140129904 | ERROR DETECTION AND CORRECTION APPARATUS, MISMATCH DETECTION APPARATUS, MEMORY SYSTEM AND ERROR DETECTION AND CORRECTION METHOD - An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected. | 05-08-2014 |
20140301132 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF - Provided is a storage control device including a history information holding unit configured to hold history information in a predetermined data area of a memory cell holding either a first value or a second value for each bit, the history information indicating which mode of a first mode or a second mode is employed upon a previous write operation, the first mode setting all bits to the first value and then setting any bit to the second value, the second mode setting all bits to the second value and then setting any bit to the first value, and a bitwise operation unit configured to perform a write operation in the second mode if the history information indicates the first mode and to perform a write operation in the first mode if the history information indicates the second mode. | 10-09-2014 |
20150026538 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails. | 01-22-2015 |