Patent application number | Description | Published |
20090016092 | SEMICONDUCTOR MEMORY DEVICE AND LOCAL INPUT/OUTPUT DIVISION METHOD - A semiconductor memory device includes: a memory cell array that is arrayed on a plurality of mats; an even number of redundancy Y-switch (YS) signal lines that are provided in three mat units and arranged in the bit line direction on the mat that is positioned in the middle among the three mats disposed continuously in the word line direction; a local input/output (LIO) line that is connected to a sense amplifier portion of the three mats, extends in the word line direction, and is divided in two in a redundancy area that is a part of the even number of redundancy Y switch signal lines; and a plurality of bit line selecting Y switch signal lines that connect bit line output of the memory cell array on the three mats to the local input/output line; wherein 8-bit data prefetch is performed from the three mats by selecting the plurality of bit line selecting Y switch signal lines and turning them ON simultaneously so as to connect the selected bit line output to each local input/output line divided in two. | 01-15-2009 |
20090116862 | IMAGE FORMING APPARATUS - Disclosed is an image forming apparatus, comprising: an image carrier; a brush to remove toner remaining on the image carrier by scrubbing a surface of the image carrier; a flicker to remove the toner adhering to the brush by contacting to the brush; a brush driving section to rotate the brush; and a control section to obtain a quantity of the toner adhering to the brush and to control the brush driving section so as to change a rotation speed of the brush based on the obtained quantity of the toner. | 05-07-2009 |
20100109163 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 05-06-2010 |
20110002159 | Semiconductor integrated circuit device - Provided are a memory array excellent in noise characteristics and small in size and a semiconductor integrated circuit device having such a memory array. | 01-06-2011 |
20120126422 | SEMICONDUCTOR DEVICE HAVING PLURAL WIRING LAYERS - A semiconductor device includes a lower wiring layer, having signal lines and power supply lines extending in a Y-direction; an upper wiring layer having signal lines and power supply lines extending in an X-direction; via conductors provided in first overlap regions where corresponding signal lines overlap each other; and via conductors provided in second overlap regions where corresponding power supply lines overlap each other. The width in the X-direction of the first regions is wider than the widths in the X-direction of the second regions. Therefore, in the first regions, a plurality of via conductors can be provided. Moreover, the power supply lines are divided in the Y-direction to avoid interference with the first regions. On a plurality of lower-layer lines, two vias are placed at a minimum pitch containing one via. | 05-24-2012 |
20130093027 | LAYOUT DATA CREATION DEVICE FOR CREATING LAYOUT DATA OF PILLAR-TYPE TRANSISTOR - A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area. | 04-18-2013 |
20130264715 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 10-10-2013 |
20140015059 | SEMICONDUCTOR DEVICE INCLUDING PILLAR TRANSISTORS - A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar. | 01-16-2014 |
20140239506 | Semiconductor Device and Manufacturing Method Thereof - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 08-28-2014 |