| Patent application number | Description | Published |
|---|
| 20100201413 | Clock control circuit and semiconductor device including the same - A clock control circuit includes a phase determination circuit that generates a first phase determination signal based on a phase of an external clock signal, a counter circuit that updates a count value based on a second phase determination signal for each sampling period, a delay line that generates an internal clock signal by delaying the external clock signal based on the count value, and an invalidation circuit that generates the second phase determination signal which is obtained by invalidating a change of the first phase determination signal within a same sampling period in response to a fact that the first phase determination circuit indicates a predetermined logical level. | 08-12-2010 |
| 20100207675 | Semiconductor device - A device includes a first circuit unit performing a detecting operation to detect a ratio of a first time period in which an input signal takes a first logic level to a second time period in which the input signal takes a second logic level. The first circuit unit includes a storing unit and storing a detection result of a detection thereby to the storing unit thereof. The device includes a first control circuit controlling the first circuit unit in response to the input signal. The device includes a current source circuit coupled to the first control circuit at a first circuit node thereof. The device includes an initialization circuit performing an initializing operation to initialize the detection result of the storing unit of the first circuit unit. The device includes a second control circuit controlling the first control circuit such that a voltage level of the first circuit node at a timing at which the initializing operation is terminated is equal to the voltage level of the first circuit node in the detecting operation following the initializing operation. | 08-19-2010 |
| 20110057697 | Clock generating circuit, semiconductor device including the same, and data processing system - To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, and a clock generating unit that generates an internal clock signal based on the second phase determination signal. The sampling circuit includes a continuity determining circuit that fixes the second phase determination signal when a logic level of the first phase determination signal changes within a sampling cycle, an initial operation circuit that fixes the second phase determination signal at a high level until when a third phase determination signal indicates a high level, and a disabling circuit that disables an operation of the continuity determining circuit after the third phase determination signal indicates a high level. | 03-10-2011 |
| 20110058437 | Clock generating circuit, semiconductor device including the same, and data processing system - A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase. | 03-10-2011 |
| 20110062998 | Semiconductor device having level shift circuit, control method thereof, and data processing system - To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data. | 03-17-2011 |
| 20110227618 | INTERNAL-CLOCK ADJUSTING CIRCUIT - A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes. | 09-22-2011 |
| 20120112829 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 05-10-2012 |
| 20120120745 | Semiconductor device and information processing system including the same - A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state. | 05-17-2012 |
| 20120124409 | SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT - A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another. | 05-17-2012 |
